Schematic readability pass, cosmetic only. Do not change any connectivity, part, value or net name.

An EE reviewer finds the schematic hard to read. Please rearrange the canvas so it reads like a printed schematic:

One clearly titled frame per functional block: Power input & rails; IEPE excitation & input protection; Analog front end & ADC; ADC clock; Teensy 4.1 carrier; Ethernet; Shutdown output (PhotoMOS, charge pump, watchdog); Front-panel LEDs; Panel connectors; TEDS (DNP).
Signal flow left to right inside each frame: inputs left, outputs right. Positive supplies at the top, ground at the bottom.
Place the frames in a logical order across the canvas, following the signal path from sensor input to ADC to Teensy to shutdown output, with power at the top or left.
Keep decoupling capacitors next to the pins they serve. Use net labels between blocks instead of long wires. Make sure no text overlaps and every designator and value is readable.
Remove the leftover isolated wire segments from deleted parts, if possible.

Before and after, report the component count (currently 328) and net count (currently 188), and confirm the netlist is unchanged. Do not start PCB layout.