# REI Balance Controller V2 — Industrial Balancing Machine Controller PCB Design Prompt ## ROLE Act as a senior mixed-signal electronics engineer, industrial PCB designer, embedded hardware architect, EMC engineer, and design-for-manufacturing reviewer. Design a production-grade industrial balancing machine controller PCB based on the reverse-engineered architecture in this repository: `https://github.com/rootcastleco/balance_soft_v2` Primary reference files: * `README.md` * `docs/siyah_kart_ee_re_detayli_analiz.md` * `docs/siyah_kart_mimarisi.md` * `docs/siyah_kart_pcb_tasarim_rehberi.md` * `docs/reconstructed_C++_communication_and_licence.md` * `aistate.md` * `systemFile.ini` * `Siyah kart hex.bin` Project name: **ROOTCASTLE REI BALANCE CONTROLLER V2** Target machine: **V-IVB-100 class industrial dynamic balancing machine** This shall be a redesigned, manufacturable replacement for the original "Siyah Kart / AFE-RDC" controller. Do not simply recreate potentially incorrect assumptions from reverse-engineering notes. All MCU pin assignments, power ratings, component footprints, isolation ratings and Ethernet PHY requirements must be verified against manufacturer datasheets before schematic finalization. --- # 1. SYSTEM OBJECTIVE Design one industrial controller board performing: 1. Two-channel vibration acquisition. 2. Rotor tacho/index pulse acquisition. 3. Rotor phase-angle calculation support. 4. RPM measurement support. 5. Ethernet communication with the host PC. 6. TCP command communication. 7. UDP real-time measurement streaming. 8. Relay outputs. 9. Isolated digital/PWM actuator outputs. 10. Optional RS485/serial service interface. 11. Persistent calibration support through MCU internal Flash. 12. SWD programming/debugging. 13. Industrial 24 VDC operation. 14. High immunity against VFD, motor, relay and solenoid EMI. The PCB itself must NOT directly switch motor phase current or VFD DC-bus power. It shall only provide isolated control signals, relay dry contacts and protected 24 V low-power outputs. --- # 2. TARGET ARCHITECTURE Use the following system architecture: ```text INDUSTRIAL 24VDC INPUT | v +---------------------------+ | Protection / EMI Filter | | Fuse / Reverse Polarity | | TVS / LC / CM filtering | +-------------+-------------+ | +------------+------------+ | | v v ISOLATED DIGITAL DC/DC ISOLATED ANALOG DC/DC 9-36V -> 3.3V 9-36V -> +/-12V | | | | DIGITAL DOMAIN ANALOG DOMAIN | | | +-------+-------+ | | | | SENSOR 1 SENSOR 2 | | | | AFE CH1 AFE CH2 | | | | LPF/AA LPF/AA | | | +---------> STM32F103VET6 <-------+ ADC3 | +----------------+----------------+ | | | SPI1 EXTI5 TIM8 | | | W5500 TACHO INPUT ISOLATED | 24V -> 3V3 OUTPUTS | MAGNETICS | RJ45 ``` --- # 3. MICROCONTROLLER Use: **STM32F103VET6** * ARM Cortex-M3 * LQFP-100 * 512 KB Flash * 64 KB SRAM * 72 MHz operation * 3.3 V supply Use an actual LQFP-100 symbol and footprint. Do not use pins that exist only in the LQFP-144 version. ### Mandatory MCU infrastructure Include: * all VDD pins * all VSS pins * VDDA * VSSA * VREF+ * VBAT * NRST * BOOT0 * SWDIO * SWCLK * optional SWO * 8 MHz HSE crystal * optional 32.768 kHz LSE * proper crystal load capacitors * local decoupling Place one 100 nF ceramic capacitor at every MCU VDD supply pair. Add local bulk: * 4.7 µF near MCU * 10 µF near MCU power entry For analog supply: ```text 3V3_DIG | ferrite bead | 3V3_A | +--100 nF +--1 µF +--4.7 µF ``` Feed VDDA/VREF from the filtered analog 3.3 V rail. --- # 4. MCU PIN MAP Treat reverse-engineered firmware pin assignments as hypotheses unless proven. Use the following clean pin allocation for the redesigned V2 board. ## SPI1 Ethernet ```text PA4 -> ETH_CS / SPI1_NSS PA5 -> ETH_SCK PA6 -> ETH_MISO PA7 -> ETH_MOSI PB0 -> ETH_INT PB1 -> ETH_RESET ``` Put optional 22-33 ohm source-series resistors on: * SCK * MOSI * CS Place them near the STM32. --- ## Analog channels Do NOT use PF3 or PF5 for ADC on STM32F103VET6 LQFP-100. Preferred assignment: ```text PC0 -> ADC3_IN10 -> VIBRATION_CHANNEL_1 PC1 -> ADC3_IN11 -> VIBRATION_CHANNEL_2 ``` Expose: ```text TP_ADC_CH1 TP_ADC_CH2 ``` immediately before MCU ADC pins. If firmware compatibility testing later proves a different ADC channel mapping, make the analog-to-MCU connection configurable through 0-ohm population options rather than redesigning the entire analog front-end. --- # 5. TACHO / INDEX INPUT Use: ```text PC5 -> EXTI5 -> TACHO_INDEX ``` Design one industrial 24 V pulse input. Connector: ```text J_TACHO 1 = +24V SENSOR 2 = TACHO SIGNAL 3 = FIELD GND 4 = SHIELD / CHASSIS ``` The signal path shall be: ```text 24V TACHO SIGNAL | TVS / surge protection | 3.3k / 0.5W current limiting | reverse protection diode | high-speed optocoupler 6N137 / equivalent | 3.3V logic | Schmitt trigger SN74LVC1G17 or equivalent | PC5 ``` Do not use a slow optocoupler as the default if it causes phase timing degradation. Target input range: **12-36 VDC** Target reliable pulse frequency: **DC to at least 10 kHz** Add test points: ```text TP_TACHO_RAW TP_TACHO_OPTO TP_TACHO_LOGIC ``` --- # 6. VIBRATION SENSOR ANALOG FRONT END Implement two physically symmetric analog channels: ```text CHANNEL A CHANNEL B ``` The two channels must have practically identical: * component topology * trace geometry * grounding * filter characteristics * gain * phase shift because phase accuracy is critical to balancing measurements. --- # 7. SENSOR INPUT CONNECTORS Provide one connector per sensor: ```text J_SENSOR_1 1 SIGNAL 2 AGND 3 SHIELD J_SENSOR_2 1 SIGNAL 2 AGND 3 SHIELD ``` Use 5.08 mm industrial pluggable terminals. Also provide optional DNP BNC footprints if PCB space allows. Sensor shield shall connect to: **CHASSIS** rather than being routed through the sensitive analog signal ground. Allow an optional RC/chassis bonding network. --- # 8. ANALOG INPUT PROTECTION Do not clamp the raw high-impedance piezo input using high-leakage protection components that would significantly affect charge measurement. Use staged protection: ```text Sensor | Series protection impedance | low leakage protection | charge / voltage amplifier | active filtering | output limiting | ADC ``` Place stronger clamping protection after the high-impedance input stage. Provide footprints for: * series resistor * low-capacitance TVS * low-leakage diode * optional RC input filtering --- # 9. CHARGE AMPLIFIER The sensor type may be piezoelectric charge-output or voltage-output. Design each input channel so its front end is configurable. Preferred low-noise JFET-input amplifier: **OPA1642 / OPA1644** Acceptable alternative: **TL074**, provided the full analog calculations and bandwidth requirements remain satisfied. Power the precision analog stage from: ```text +12VA -12VA AGND ``` Provide configurable feedback components: ```text RF1 CF1 RF2 CF2 ``` with parallel footprints to permit calibration to the actual sensor charge sensitivity. Do not permanently optimize the charge amplifier for a sensor sensitivity that has not yet been measured. Provide 0-ohm/DNP bypass options allowing voltage-output accelerometers to bypass the charge-amplifier configuration. --- # 10. ANTI-ALIAS FILTER After each input amplifier, implement at least: **2nd-order active low-pass anti-alias filter** Prefer provision for a 4th-order implementation if board area allows. Nominal default cutoff: **approximately 10 kHz** but make cutoff configurable through resistor/capacitor population. Provide component options for approximately: * 2 kHz * 5 kHz * 10 kHz Do not blindly choose filter values. Calculate: * Q * cutoff frequency * gain * phase response * resistor thermal noise * op-amp GBW requirement Include these calculations in the design documentation. --- # 11. ADC LEVEL CONDITIONING STM32 ADC input may only see the MCU analog supply range. Never directly connect a bipolar +/-12 V op-amp output to an STM32 ADC pin. Convert the bipolar vibration waveform to a 0-3.3 V ADC-compatible signal. Generate a low-noise reference: ```text VBIAS = approximately 1.65 V ``` using either: * precision reference + buffer or * resistor divider + low-noise op-amp buffer Do not use an unloaded resistor divider as the sole precision reference for both AFE channels. Final ADC waveform shall be centered around approximately: ```text 1.65 V ``` with maximum expected signal contained inside approximately: ```text 0.1 V to 3.2 V ``` under normal operation. Add: * 100-330 ohm ADC series resistor * small ADC input capacitor * low-leakage clamps to analog rails Place this network immediately adjacent to the MCU ADC pin. --- # 12. ANALOG CHANNEL TEST POINTS Each channel shall expose: ```text TP_SENS1_RAW TP_SENS1_CHARGE TP_SENS1_FILTER TP_ADC_CH1 TP_SENS2_RAW TP_SENS2_CHARGE TP_SENS2_FILTER TP_ADC_CH2 TP_VBIAS TP_VREF TP_AGND ``` All analog test points must be accessible using an oscilloscope probe without disassembling other parts. --- # 13. ETHERNET For the new Rootcastle firmware architecture, use: **W5500** unless analysis of the original firmware proves that an ENC28J60-compatible driver must be preserved. If existing dumped firmware must execute without modification: **STOP THE DESIGN BEFORE FINALIZING THE ETHERNET SECTION UNTIL THE ORIGINAL CONTROLLER IC HAS BEEN PHYSICALLY OR FIRMWARE-LEVEL IDENTIFIED.** W5500 block shall contain: * W5500 * 25 MHz crystal * required load capacitors * proper bias/termination network * local 100 nF decoupling * local bulk capacitance * hardware reset * INT output * SPI interface * integrated-magnetics RJ45 or external magnetics * Ethernet ESD protection Use an industrial MagJack such as: **HR911105A or verified equivalent** provided its pinout matches the Ethernet controller reference design. Do not assume MagJack footprints are interchangeable. --- # 14. ETHERNET ROUTING From Ethernet PHY/controller to magnetics: * maintain approximately 100-ohm differential impedance * route TX+/TX- as a differential pair * route RX+/RX- as a differential pair * minimize stubs * avoid vias where practical * length-match within sensible Ethernet constraints * keep away from switching power and relay nodes * no ground-plane discontinuity underneath the PHY-side differential signals unless required by the manufacturer's reference layout RJ45 shield shall connect to: ```text CHASSIS ``` not directly to quiet analog ground. Allow optional bonding: ```text CHASSIS -- 1 nF HV capacitor -- DGND CHASSIS -- 1 MΩ -- DGND ``` subject to final EMC strategy. --- # 15. NETWORK SOFTWARE COMPATIBILITY Hardware and firmware architecture must support: ```text Default controller IP: 192.168.3.111 Host-side network: 192.168.3.x TCP control port: 1006 UDP measurement destination/listening port: 2222 ``` Current host architecture expects real-time UDP measurements and a TCP control channel. Existing simulator models commands: ```text 0x0101 START 0x0102 STOP 0x0103 SET SPEED ``` Preserve the ability to support this host protocol. This is primarily a firmware requirement, but do not select an Ethernet controller that prevents the existing communication architecture from being implemented. --- # 16. SERIAL SERVICE INTERFACE Provide USART2: ```text PA2 = USART2_TX PA3 = USART2_RX ``` Route first to a service header: ```text J_UART 1 3V3 2 GND 3 TX 4 RX ``` Additionally provide an optional industrial RS485 transceiver. Preferred: **MAX3485 / equivalent 3.3 V RS485 transceiver** Include: * A/B TVS protection * selectable 120-ohm termination * bias resistors through DNP footprints * DE/RE MCU control * screw terminal Do not permanently terminate the RS485 bus unless selected through jumper/population option. --- # 17. TIM8 / VFD / ACTUATOR CONTROL Reserve: ```text PC6 = TIM8_CH1 PC7 = TIM8_CH2 ``` for isolated control/PWM outputs. Do NOT directly drive a motor gate stage. Create: ```text PWM_OUT_1 PWM_OUT_2 ``` through high-speed optocouplers or digital isolators. Output side shall support industrial control interfaces such as: * open collector * open drain * isolated logic pulse Provide a terminal block and field-side 24 V reference where required. Do not connect VFD control ground directly into the quiet ADC ground. --- # 18. RELAY OUTPUTS Use two 24 V relays: ```text RL1 RL2 ``` Reference part: **Omron G5T-1A 24VDC** or a footprint-compatible verified equivalent. MCU controls: ```text PE0 -> RELAY1 PE1 -> RELAY2 ``` Driver topology: ```text MCU GPIO | 1k resistor | BC817 NPN | relay coil | 24V ``` Add: * 10k base-emitter pull-down * flyback diode * relay status LED * LED resistor Use a suitable flyback diode such as: * SS14 * 1N400x * equivalent rather than relying on an undersized signal diode. --- # 19. RELAY CONTACT SAFETY Bring relay contacts to separate edge-mounted terminal blocks. Use: ```text COM NO ``` for each relay. No low-voltage signal traces shall pass: * between relay contact pins * under high-voltage contact regions * through contact-to-coil isolation areas If relay contacts may switch mains: maintain a conservative physical isolation zone and design creepage/clearance according to the applicable IEC standard, working voltage, pollution degree and overvoltage category. Until those parameters are confirmed, reserve approximately: **8 mm physical isolation** between potentially mains-connected relay copper and SELV electronics. Add milled slots where useful. --- # 20. OPTIONAL 24 V SOLENOID OUTPUTS Add two optional low-side field outputs: ```text OUT1_SOLENOID OUT2_SOLENOID ``` Use at least: * 60 V rated N-channel MOSFET * gate resistor * gate pull-down * flyback path * TVS protection * output LED * test point Do not use AO3400 for an unknown industrial inductive 24 V load unless current, dissipation and transient calculations prove it adequate. Select MOSFET ratings based on the actual load. Mark these channels DNP until load current is known. --- # 21. POWER INPUT Input specification: ```text Nominal: 24 VDC Operating design target: 9-36 VDC ``` Connector: ```text J_PWR 1 VIN+ 2 VIN- 3 CHASSIS / PE optional ``` Input chain: ```text 24V connector | replaceable fuse / resettable protection | reverse-polarity protection | TVS | common-mode / differential EMI filtering | bulk capacitance | DC/DC modules ``` Use a reverse-polarity MOSFET/ideal-diode implementation where practical rather than wasting significant power in a simple series diode. --- # 22. INPUT SURGE PROTECTION Because the nominal input may reach 36 V, select the TVS standoff voltage accordingly. Do not place a 24 V TVS with a working voltage below the valid maximum supply voltage. Use a suitably rated industrial TVS after calculation. Example design family: ```text SMBJ36A / SMBJ40A class ``` subject to actual system transient requirements. Include: * fuse * TVS * pi filter * bulk low-ESR electrolytic * ceramic bypass Design PCB footprints with adequate copper area for surge current. --- # 23. ISOLATED POWER Preferred reference architecture from the reverse-engineered board: ### Digital ```text PWR1: Delta DJ06S2403A 9-36 VDC input 3.3 V isolated output approximately 6 W ``` ### Analog ```text PWR2: Delta DJ06D2412A 9-36 VDC input +12 V / 0 / -12 V isolated output approximately 6 W ``` If these exact modules are unavailable: select industrial isolated DC/DC replacements with: * equal or greater input range * adequate power * verified isolation voltage * industrial temperature rating * real manufacturer datasheet * obtainable footprint Do not invent a DC/DC footprint. --- # 24. GROUND ARCHITECTURE Use three conceptual ground domains: ```text CHASSIS QUIET SYSTEM GROUND FIELD / PRIMARY RETURN ``` Within the isolated low-voltage secondary system, do NOT create arbitrary long splits in the PCB reference plane that force digital currents around gaps. For the MCU and ADC region: * use disciplined mixed-signal placement * keep analog return currents local * keep digital return currents away from AFE * use a solid reference plane where possible * filter VDDA independently If separate schematic nets AGND and DGND are used, provide one deliberate connection point close to the ADC/VSSA reference region using: ```text 0-ohm resistor or ferrite bead population option ``` No sensitive analog trace may cross a ground split. No high-speed SPI trace may cross a ground split. --- # 25. PCB LAYER STACK Use a minimum 4-layer PCB. Recommended: ```text L1: Components + signal L2: Solid reference ground L3: Power distribution + slow signals L4: Signal + components ``` Material: ```text FR-4 1.6 mm 1 oz copper minimum ``` If relay/solenoid current calculations require it, increase copper appropriately. --- # 26. PLACEMENT ZONES Create explicit functional placement zones. ## Zone A — Analog Contains: * sensor connectors * charge amplifiers * anti-alias filters * VBIAS * analog test points Keep this region physically distant from: * W5500 crystal * switching power * relay coils * MOSFET outputs * tacho field wiring * VFD control outputs --- ## Zone B — MCU Central position containing: * STM32F103VET6 * HSE * SWD * reset * boot * VDDA filtering * ADC input RC --- ## Zone C — Ethernet Near PCB edge: * W5500 * crystal * magnetics * RJ45 * ESD Keep PHY-to-RJ45 route extremely short. --- ## Zone D — Power Near 24 V input: * fuse * reverse-polarity stage * TVS * filters * isolated DC/DC modules Do not route switching current through the analog area. --- ## Zone E — Field Outputs At the opposite edge from the sensor inputs: * relays * solenoid MOSFETs * VFD outputs * field terminals --- # 27. CONNECTOR LAYOUT All field connectors should be reachable from board edges. Suggested edge sequence: ```text LEFT: Sensor 1 Sensor 2 Tacho TOP: RJ45 SWD Service UART RIGHT: Relay 1 Relay 2 PWM/VFD outputs RS485 BOTTOM: 24V input Optional solenoid outputs Expansion connector ``` --- # 28. EXPANSION CONNECTOR Provide a 2x20 or equivalent IDC expansion header. Expose spare: * GPIO * SPI * I2C * UART * 3.3V * 24V protected supply * DGND * optional analog signals Never expose raw unprotected MCU ADC inputs directly to external industrial wiring. Clearly mark reserved pins. --- # 29. DEBUG AND PROGRAMMING Add standard SWD: ```text SWDIO SWCLK NRST 3V3 GND optional SWO ``` Use either: * ARM Cortex 10-pin 1.27 mm or * robust 2.54 mm development header depending manufacturing preference. Include BOOT0 test/jumper option. Default BOOT0 state: **LOW** --- # 30. STATUS INDICATORS Add LEDs for: ```text 24V INPUT 3V3 DIGITAL +12VA -12VA MCU HEARTBEAT FAULT ETH LINK ETH ACT RELAY1 RELAY2 ``` Do not place blinking digital LED currents inside the analog front-end return path. Use independent current-limiting resistors. --- # 31. TEST POINTS Mandatory test points: ```text TP_24VIN_RAW TP_24VIN_PROTECTED TP_3V3 TP_3V3A TP_P12VA TP_N12VA TP_DGND TP_AGND TP_CHASSIS TP_VREF TP_VBIAS TP_ADC_CH1 TP_ADC_CH2 TP_TACHO_RAW TP_TACHO_OPTO TP_TACHO_LOGIC TP_ETH_SCK TP_ETH_MOSI TP_ETH_MISO TP_ETH_CS TP_ETH_INT TP_ETH_RESET TP_RELAY1 TP_RELAY2 TP_USART_TX TP_USART_RX ``` --- # 32. CURRENT MEASUREMENT HOOKS Place 0-ohm links or suitable current-measurement jumpers on: ```text 3V3 MCU rail Ethernet rail Analog +12V Analog -12V ``` so each subsystem's consumption can be measured during bring-up. --- # 33. TRACE WIDTH GUIDELINES Do not use one arbitrary trace width globally. At minimum calculate widths for: ```text 24V input relay coil currents solenoid currents DC/DC feeds 3V3 power analog power signals ``` Starting guidelines only: ```text 24V distribution: >=1.0 mm where appropriate relay/field power: >=1.0 mm 3V3 main distribution: approximately 0.5 mm analog rails: approximately 0.4-0.5 mm normal signals: approximately 0.2-0.25 mm ``` Increase according to IPC current calculations. --- # 34. HIGH-SPEED SIGNAL RULES SPI: * keep short * route over continuous ground * avoid analog front-end * SCK requires highest routing priority * optional source termination * avoid unnecessary vias Ethernet: * differential pairs * controlled impedance * continuous reference where required * minimal stubs * maintain manufacturer reference topology Crystals: * place directly adjacent to IC * very short traces * symmetric routing * ground guard/keepout where recommended * no high-current trace beneath crystal network --- # 35. ANALOG ROUTING RULES Sensor signal traces: * minimum length * no relay/PWM/SPI parallel routing * surrounded by quiet reference where appropriate * no switching regulator underneath * no Ethernet underneath * no digital clock underneath Place charge amplifier as close as possible to the sensor connector. The highest impedance node must be physically the shortest node in the analog section. --- # 36. EMC DESIGN Design toward industrial EMC robustness. Address at least: * ESD * EFT/burst * conducted RF * VFD-generated common mode noise * relay inductive transients * solenoid transients * cable shield currents * Ethernet cable discharge events Use: * TVS * ferrite beads * common-mode chokes when appropriate * short return paths * chassis bonding * RC filters * shield termination Do not solve EMC problems simply by adding random ferrite beads. Every ferrite must have a defined noise-current path and purpose. --- # 37. MECHANICAL PCB Mechanical dimensions of the original board are NOT considered verified from the repository. Therefore: create the PCB outline as a parameter. Use provisional prototype dimensions: ```text 160 mm x 100 mm ``` until actual chassis measurements are provided. Use four mounting holes: ```text M3 3.2 mm finished hole ``` Maintain adequate edge clearance. Position mounting holes approximately 5 mm from edges unless mechanical constraints dictate otherwise. Provide optional chassis-connected copper around mounting holes. Do not finalize production mounting coordinates without measurement of the actual machine enclosure. --- # 38. SILKSCREEN Use: ```text ROOTCASTLE ENGINEERING & INNOVATION REI BALANCE CONTROLLER V2 REV: A ``` Include readable connector labels. Mark: * polarity * relay COM/NO * sensor channel * Tacho * 24 V * RS485 A/B * SWD pin 1 * board revision * serial-number area Prefer matte black soldermask with white silkscreen if manufacturing permits. --- # 39. DESIGN FOR MANUFACTURING Prefer: * 0603 or 0805 passives * THT for industrial field connectors * THT for relays * THT for isolated DC/DC modules * LQFP MCU * easily inspectable packages Avoid unnecessary: * BGA * exotic components * 0201 * blind vias * buried vias * via-in-pad unless electrically required. Target standard low-cost 4-layer PCB fabrication. --- # 40. COMPONENT REQUIREMENTS Every component in the BOM must have: * actual manufacturer * actual manufacturer part number * verified voltage/current rating * verified package * verified footprint * datasheet source * lifecycle/status where available Do not create fictitious component numbers. If exact component availability is unknown: mark: ```text TBD / DNP / ALTERNATE ``` instead of inventing a part. --- # 41. FIRMWARE COMPATIBILITY RULE There are two possible product modes. ## MODE A — Rootcastle V2 firmware Preferred. The PCB may use: * corrected MCU pin assignments * W5500 * improved analog conditioning * high-speed tacho isolation and the firmware HAL will be modified accordingly. ## MODE B — Original dumped firmware If `Siyah kart hex.bin` must run without modification: DO NOT assume the proposed pin map or W5500 is compatible. Before PCB release, determine from firmware disassembly or original-board measurements: * exact ADC channels * exact Ethernet controller * Ethernet CS pin * Ethernet reset pin * Ethernet interrupt pin * relay GPIO * TIM8 outputs * tacho GPIO * USART assignment * oscillator configuration Mark all unresolved binary-compatibility items as: ```text REQUIRES HARDWARE/FIRMWARE VERIFICATION ``` A visually correct PCB that cannot execute the original firmware is considered a failed design. --- # 42. SCHEMATIC STRUCTURE Generate hierarchical schematic sheets: ```text 00_SYSTEM 01_POWER_INPUT 02_ISOLATED_POWER 03_MCU 04_ANALOG_CHANNEL_A 05_ANALOG_CHANNEL_B 06_TACHO 07_ETHERNET 08_SERIAL_RS485 09_RELAY_OUTPUTS 10_FIELD_OUTPUTS 11_DEBUG_EXPANSION ``` No monolithic one-page schematic. --- # 43. NET NAMING Use explicit descriptive names. Examples: ```text VIN_24V_RAW VIN_24V_PROTECTED 3V3_DIG 3V3_A P12V_A N12V_A DGND AGND CHASSIS VBIAS_1V65 ADC_VREF SENS1_RAW SENS1_AFE ADC_CH1 SENS2_RAW SENS2_AFE ADC_CH2 TACHO_FIELD TACHO_ISO TACHO_LOGIC ETH_CS ETH_SCK ETH_MISO ETH_MOSI ETH_INT ETH_RST RELAY1_CTRL RELAY2_CTRL PWM1_CTRL PWM2_CTRL ``` Avoid meaningless net names such as `Net-(U1-Pad47)` in the released design. --- # 44. REQUIRED DESIGN CALCULATIONS Before PCB release provide calculations for: 1. 24 V input current. 2. DC/DC power margin. 3. MCU current. 4. Ethernet current. 5. relay coil current. 6. solenoid output current. 7. TVS selection. 8. input fuse selection. 9. trace current capacity. 10. charge amplifier gain. 11. analog filter cutoff. 12. op-amp noise. 13. ADC full-scale margin. 14. ADC source impedance. 15. tacho optocoupler current. 16. tacho timing bandwidth. 17. Ethernet impedance strategy. 18. creepage/clearance. --- # 45. THREAT / FAILURE MODEL Analyze at least these hardware failures: ```text Reverse 24V polarity 36V continuous input 24V surge Open sensor Shorted sensor Sensor cable ESD Tacho overvoltage Missing tacho Relay coil short Relay transient Solenoid transient Ethernet ESD Ethernet unplug during measurement 3V3 brownout +12V rail missing -12V rail missing MCU watchdog reset SPI Ethernet lockup Ground potential difference VFD common-mode interference ADC overvoltage ``` The board should fail safely. A peripheral failure must not expose the MCU ADC or host PC to field voltage. --- # 46. OBSERVABILITY Hardware shall allow firmware to diagnose as much as practical. Provide options to monitor: * 24 V input presence * 3.3 V rail presence * analog rail presence * Ethernet reset * Ethernet interrupt * relay commanded state * optional output fault signals Where useful, expose rail monitoring through resistor dividers to spare MCU ADC channels. --- # 47. BRING-UP STRATEGY Generate a bring-up procedure in this order: ```text 1. Visual inspection 2. Resistance-to-ground checks 3. Current-limited 24V power-up 4. Verify protected VIN 5. Verify 3V3 6. Verify +12V 7. Verify -12V 8. Verify MCU reset 9. Program minimal test firmware 10. Verify crystal 11. Verify SWD 12. Verify UART 13. Verify Ethernet SPI 14. Establish Ethernet link 15. Test TCP 1006 16. Test UDP 2222 17. Inject tacho pulse 18. Measure EXTI timing 19. Inject analog sine wave CH1 20. Inject analog sine wave CH2 21. Verify ADC amplitude 22. Verify channel phase matching 23. Switch relay outputs 24. Confirm no MCU reset 25. Test field outputs 26. Perform EMI/noise evaluation ``` --- # 48. TEST REQUIREMENTS ## Power Test: ```text VIN = 9V VIN = 12V VIN = 24V VIN = 30V VIN = 36V ``` No rail shall exceed IC absolute maximum ratings. --- ## Analog With sensor inputs shorted using the proper source impedance: target ADC-domain noise: ```text < approximately 2 mV RMS ``` unless analysis establishes a more appropriate requirement. Inject calibrated sine signals across the usable frequency range. Measure: * gain * offset * noise * phase * clipping * channel-to-channel phase mismatch --- ## Tacho Inject: ```text 12 V 24 V 36 V ``` pulse levels. Frequency sweep: ```text 1 Hz -> 10 kHz ``` Confirm: * no double triggers * stable rising edge * no missed pulses * bounded timing jitter --- ## Ethernet Test: * power-cycle recovery * cable disconnect/reconnect * host reconnect * continuous UDP streaming * TCP command traffic during UDP streaming * 24-hour soak --- ## Outputs Switch relay and field outputs while ADC acquisition operates. Requirements: * no MCU reset * no Ethernet reset * no permanent ADC corruption * no tacho false trigger --- # 49. PCB ACCEPTANCE CRITERIA Do not consider the design complete until: * ERC = zero unexplained errors * DRC = zero errors * all power pins are connected correctly * all decoupling is present * no critical unconnected nets * MCU pin mapping verified against datasheet * Ethernet controller pinout verified * MagJack pinout verified * DC/DC footprint verified * relay footprint verified * analog filter mathematically verified * ADC never exceeds MCU supply rails * no signal crosses an isolation gap * no sensitive analog signal crosses a ground split * no relay contact routing violates isolation constraints * all critical signals have test points * SWD is accessible * connector polarity is explicitly marked --- # 50. REQUIRED OUTPUT FILES Produce: 1. System block diagram. 2. Assumption list. 3. Unresolved-item list. 4. Hierarchical schematic. 5. Complete PCB layout. 6. PCB stackup. 7. BOM with manufacturer part numbers. 8. Netlist. 9. Firmware pin-map table. 10. Test-point table. 11. ERC report. 12. DRC report. 13. Gerber files. 14. NC drill files. 15. Pick-and-place. 16. BOM CSV. 17. Assembly drawing. 18. 2D fabrication drawing. 19. 3D PCB render. 20. STEP model. 21. Bring-up checklist. 22. Production test procedure. 23. Failure-mode review. 24. Revision-controlled README. --- # 51. STOP CONDITIONS Do not silently guess critical unknowns. Stop and mark a requirement unresolved if any of the following cannot be proven: * original Ethernet IC * original PCB mechanical dimensions * sensor charge sensitivity * sensor wiring standard * relay contact working voltage * solenoid current * exact binary firmware pin mapping Use: ```text TBD — REQUIRES MEASUREMENT ``` rather than inventing a value. --- # FINAL DESIGN PRIORITY Prioritize in this exact order: ```text 1. Electrical safety 2. Measurement integrity 3. Firmware compatibility 4. EMI immunity 5. Deterministic timing 6. Serviceability 7. Manufacturability 8. Cost 9. PCB aesthetics ``` The resulting board must be an engineering instrument, not merely a PCB that looks plausible. Before routing begins, first output: 1. architecture, 2. final proposed pin map, 3. power tree, 4. analog signal-chain calculations, 5. unresolved assumptions, and only then generate the schematic and PCB.