# Flux.ai PCB Design Prompt — WalkInPeace v1.0
## 8-Channel Bilateral EMG Gait-Freeze Prediction Wearable

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## 1. BOARD OVERVIEW

Design a two-layer FR4 PCB named **WalkInPeace Main Board v1.0**.

- **Board dimensions:** 85 mm × 55 mm
- **Layer stack:** TOP signal/power | FR4 1.6 mm core | BOTTOM ground plane
- **Copper weight:** 1 oz (35 µm) both layers
- **Min trace width:** 0.15 mm signal, 0.4 mm power
- **Min clearance:** 0.15 mm
- **Min via drill:** 0.3 mm; via pad 0.6 mm
- **Solder mask:** both sides, green
- **Silkscreen:** both sides, white
- **Finish:** ENIG (Electroless Nickel Immersion Gold)
- **Impedance control:** not required (EMG operates below 500 Hz)
- **Design standard:** IPC-2221 Class 2

The PCB is a wearable medical-adjacent biosignal acquisition device worn at the waist inside a 3D-printed belt-clip enclosure. It has no mains connection. All power comes from a single-cell 3.7 V LiPo battery. Total worn weight target is under 140 g.

---

## 2. COMPONENT LIST (exact parts)

| Ref | Part | Description | Package |
|-----|------|-------------|---------|
| U1 | Texas Instruments ADS1299IPAGR | 8-channel 24-bit biosignal ADC, 500 SPS/ch, integrated PGA and bias drive | TQFP-64, 10×10 mm, 0.5 mm pitch |
| U2 | Espressif ESP32-S3-WROOM-1-N8R8 | Wi-Fi+BLE5 SoC module, 8 MB Flash, 8 MB PSRAM, castellated pads | 18×25.5 mm stamp module |
| U3 | InvenSense MPU-6050 | 6-axis IMU, I2C, 400 kHz fast mode | QFN-24, 4×4 mm |
| U4 | Texas Instruments DRV2605LDGSR | Haptic driver for LRA/ERM, I2C | VSSOP-10 |
| U5 | Texas Instruments TP4056 | Single-cell LiPo linear charger, up to 1 A | SOP-8 |
| U6 | Diodes Inc AP2112K-3.3TRG1 | 600 mA LDO regulator, 3.3 V fixed output, very low dropout | SOT-25 |
| U7 | Zetex FMMT617TA | NPN transistor, 20 V, 1 A, for buzzer drive | SOT-23 |
| J1 | USB Type-C receptacle | 16-pin, through-hole or SMD, 5 V input for charging | USB-C SMD |
| J2–J9 | Würth 691311500008 | 8× 2-pin 2.54 mm pitch screw terminal blocks | Through-hole |
| J10 | JST PH 2-pin SMD | LiPo battery connector, 2 mm pitch | JST-PH SMD |
| J11 | JST PH 2-pin SMD | LRA motor connector | JST-PH SMD |
| J12 | 2-pin 2.54 mm header | Buzzer connector | Pin header |
| J13 | 4-pin 2.54 mm header | JTAG/UART debug header | Pin header |
| D1 | Green LED 0603 | Charge status indicator | 0603 |
| D2 | Red LED 0603 | Fault/power indicator | 0603 |
| D3 | Schottky diode SS14 | Reverse-polarity protection on battery input | SMA |
| BZ1 | Active piezo buzzer | 3–5 V, 90 dB @ 10 cm, 12 mm diameter, self-oscillating | Through-hole 12 mm |
| SW1 | Tactile pushbutton | Power on/off and mode select, 6×6 mm | Through-hole |
| SW2 | SPDT slide switch | Battery disconnect | Through-hole |
| All resistors/capacitors | Standard | See netlist below | 0402 SMD unless stated |

---

## 3. POWER ARCHITECTURE

### 3.1 Charging Path

USB-C J1 VBUS (5 V) → TP4056 U5 VIN pin.

**TP4056 connections (U5):**
- VIN → 5 V from USB-C VBUS. Add 10 µF + 0.1 µF bypass capacitors from VIN to GND.
- BAT → JST battery connector J10 positive terminal via Schottky diode D3 (anode=BAT, cathode=J10+). This provides reverse-polarity protection.
- PROG pin → 2 kΩ resistor to GND (sets charge current = 500 mA; appropriate for 1500 mAh cell at 0.33C).
- CHRG (open-drain, active low when charging) → 1 kΩ → D1 (green LED) → 3.3V_ALWAYS rail. (CHRG asserted = LED on.)
- STDBY (open-drain, active low when full) → 1 kΩ → D2 (red LED) → 3.3V_ALWAYS rail.
- TE pin → GND (disables timer for safety).
- GND → GND plane.

### 3.2 System Power Rail

Battery positive (VBAT, ~3.7–4.2 V nominal) → SW2 (battery disconnect slide switch) → AP2112K-3.3 LDO U6 input (VIN).

**AP2112K-3.3 U6 connections:**
- VIN → VBAT_SW (switched battery positive after SW2). Add 10 µF ceramic + 1 µF ceramic from VIN to GND.
- VOUT → 3V3 rail. Add 10 µF ceramic + 0.1 µF ceramic from VOUT to GND, placed within 1 mm of U6 output.
- EN → VOUT (tie high; always enabled when powered).
- GND → GND plane.

The **3V3 rail** supplies: ESP32-S3 module (U2), MPU-6050 (U3), DRV2605L (U4), buzzer transistor (U7), LEDs, and the ADS1299 digital supply (DVDD and all digital IO).

### 3.3 ADS1299 Analog Supply (AVDD)

The ADS1299 analog supply must be clean. Create a filtered analog supply:

**3V3 → L1 (ferrite bead BLM18AG601SN1D, 600 Ω @ 100 MHz, 0402) → AVDD_FILT node.**

From AVDD_FILT to AGND: 10 µF tantalum (C_AV1) + 1 µF ceramic (C_AV2) + 100 nF ceramic (C_AV3) + 10 nF ceramic (C_AV4). These four capacitors form the analog supply decoupling bank for ADS1299 AVDD/AVSS pins.

AVDD_FILT connects to all ADS1299 AVDD pins (there are multiple; connect all of them together at this node).

### 3.4 Ground Planes

- BOTTOM layer: **solid DGND copper pour** covering 100% of board area below digital components.
- TOP layer: **AGND copper pour** covering the analog region (ADS1299 and electrode connector area, approximately left 40% of board).
- AGND and DGND connect at **exactly one point**: a 0 Ω link resistor R_GND (0402) placed directly adjacent to ADS1299 AVSS pins.
- Do NOT connect AGND and DGND anywhere else on the board.

---

## 4. ADS1299 SCHEMATIC (U1)

### 4.1 ADS1299 Power and Bypass

Connect all AVDD pins to AVDD_FILT node. Connect all AVSS pins to AGND.

**DVDD pin (U1 internal 1.8 V digital LDO output):**
- DVDD → 10 µF ceramic (C_DV1) to DGND.
- DVDD → 100 nF ceramic (C_DV2) to DGND.
- Place C_DV1 and C_DV2 within 1 mm of DVDD pin.
- Do NOT supply DVDD externally; the ADS1299 generates it internally.

All DGND pins → DGND plane.

**VCAP pin (internal reference buffer bypass):**
- VCAP → 10 µF ceramic (C_VCAP) to AVSS/AGND.

### 4.2 ADS1299 Reference

**Internal voltage reference (2.4 V nominal):**
- VREFP → 10 µF ceramic (C_REF1) + 100 nF ceramic (C_REF2) to AVSS.
- VREFN → AVSS (GND). This sets the reference voltage to 2.4 V using internal reference.
- Place both capacitors within 1 mm of VREFP pin.

### 4.3 ADS1299 BIAS Circuit

The BIAS circuit provides patient reference (right-leg drive equivalent):

- BIASOUT → 10 kΩ (R_BIAS) → BIAS_ELEC net (single-wire). Connect BIAS_ELEC to pin 1 of J10_BIAS dedicated 2-pin header (J_BIAS, separate from J1–J9 EMG connectors, labelled "BIAS ELECTRODE"). This connects to the patient reference electrode placed over the patella bony landmark.
- BIASREF → 100 nF ceramic (C_BIASREF) to AVSS. Also connect BIASREF through 10 kΩ + 10 kΩ resistor divider between AVDD_FILT and AVSS (AVDD_FILT → R_BREF1 10 kΩ → BIASREF → R_BREF2 10 kΩ → AVSS). This sets BIASREF to mid-supply (~1.65 V).
- BIASIN → AVSS (internal bias amplifier input for common mode; tie low for simple configuration).

### 4.4 ADS1299 SRB (Reference Switch)

- SRB1 → no connection (NC). Leave floating.
- SRB2 → SRB2_NET. Route SRB2_NET to a 0 Ω optional link pad. By default leave open (true differential mode for bilateral EMG).

### 4.5 ADS1299 Electrode Inputs (8 Differential Channels)

**Channel assignment (muscle mapping):**

| Ch | INxP | INxN | Connector | Muscle |
|----|------|------|-----------|--------|
| 1 | IN1P | IN1N | J2 | Left Tibialis Anterior (L_TA+, L_TA-) |
| 2 | IN2P | IN2N | J3 | Left Gastrocnemius Medialis (L_GM+, L_GM-) |
| 3 | IN3P | IN3N | J4 | Left Vastus Lateralis (L_VL+, L_VL-) |
| 4 | IN4P | IN4N | J5 | Left Biceps Femoris (L_BF+, L_BF-) |
| 5 | IN5P | IN5N | J6 | Right Tibialis Anterior (R_TA+, R_TA-) |
| 6 | IN6P | IN6N | J7 | Right Gastrocnemius Medialis (R_GM+, R_GM-) |
| 7 | IN7P | IN7N | J8 | Right Vastus Lateralis (R_VL+, R_VL-) |
| 8 | IN8P | IN8N | J9 | Right Biceps Femoris (R_BF+, R_BF-) |

**For each differential channel (repeat for all 8):**
- INxP → 1 MΩ (R_PROTxP, input protection resistor) → Jx pin 1 (positive electrode lead).
- INxN → 1 MΩ (R_PROTxN, input protection resistor) → Jx pin 2 (negative electrode lead).
- Between INxP and INxN (after protection resistor, before ADS1299 pin): 47 pF (C_DIFFx) differential capacitor. This is an anti-aliasing/EMI suppression cap connected between the two differential nodes as close as possible to the ADS1299 pins.
- INxP → 10 nF (C_CMx_P) to AGND (common-mode bypass).
- INxN → 10 nF (C_CMx_N) to AGND (common-mode bypass).

This RCC front-end forms: 1 MΩ + 47 pF differential + 10 nF common-mode = classic 3-element EMG input filter matching SENIAM recommendations.

### 4.6 ADS1299 GPIO Pins

- GPIO1, GPIO2, GPIO3, GPIO4 → route to test pads TP_GPIO1–TP_GPIO4 (1 mm circular pads). No other connection; leave floating for Phase B expansion.

### 4.7 ADS1299 Control Signals (to ESP32-S3)

| ADS1299 Signal | Net Name | ESP32-S3 GPIO |
|----------------|----------|---------------|
| SCLK | SPI_SCLK | GPIO12 |
| DIN | SPI_MOSI | GPIO11 |
| DOUT | SPI_MISO | GPIO13 |
| CS (active low) | ADS_CS_N | GPIO10 |
| DRDY (active low) | ADS_DRDY_N | GPIO9 |
| RESET (active low) | ADS_RESET_N | GPIO8 |
| START | ADS_START | GPIO7 |
| PWDN (active low) | ADS_PWDN_N | GPIO6 |
| CLKSEL | ADS_CLKSEL | tie to DVDD via 10 kΩ (logic HIGH = internal oscillator enabled) |
| CLK | NC | No connection |

All SPI and control signals are **3.3 V logic** (ADS1299 DVDD = 1.8 V internal, but the IO threshold is referenced to DVDD and accepts 3.3 V logic because the ADS1299 is 3.3 V IO-tolerant — verify in datasheet; add 33 Ω series resistors R_SPI_x on each SPI trace as signal integrity protection).

Add 33 Ω series resistors on: SPI_SCLK, SPI_MOSI, SPI_MISO, ADS_CS_N (at the driving end, close to ESP32-S3 pads).

Add a 10 kΩ pull-up from ADS_CS_N to 3V3 to ensure CS defaults high on startup.
Add a 10 kΩ pull-up from ADS_RESET_N to 3V3 (active-high default = not in reset).
Add a 10 kΩ pull-up from ADS_PWDN_N to 3V3 (active-high default = powered on).
Add a 10 kΩ pull-down from ADS_DRDY_N line (so DRDY reads defined logic when ADS1299 is held in reset).

---

## 5. ESP32-S3-WROOM-1 MODULE (U2)

Use the ESP32-S3-WROOM-1-N8R8 stamp module. Solder all castellated pads to corresponding PCB pads. Provide 2.54 mm pad pitch on PCB footprint matching the module datasheet.

**Module power:**
- Module 3V3 pin → 3V3 rail. Add 100 µF electrolytic (C_ESP_BULK, radial through-hole or SMD 1206) + 10 µF ceramic + 100 nF ceramic to GND, within 3 mm of module power pins.
- Module GND pins (multiple) → DGND plane. Connect all module GND pads.
- Module EN (chip enable) → 10 kΩ pull-up to 3V3 (always enabled). Add 100 nF from EN to GND.
- Module IO0 → 10 kΩ pull-up to 3V3. Also route IO0 to SW1 pin 1; SW1 pin 2 → GND (boot mode button: press to pull IO0 low at power-on for flash download mode).

**Module RF antenna:**
- Keep 15 mm keep-out zone (no copper pours, no traces, no components) under and around the PCB antenna area on the top-right corner of the ESP32-S3 module.

**GPIO assignments:**

| GPIO | Function | Net | Notes |
|------|----------|-----|-------|
| GPIO4 | I2C SDA | I2C_SDA | 4.7 kΩ pull-up to 3V3 |
| GPIO5 | I2C SCL | I2C_SCL | 4.7 kΩ pull-up to 3V3 |
| GPIO6 | ADS1299 PWDN | ADS_PWDN_N | Output |
| GPIO7 | ADS1299 START | ADS_START | Output |
| GPIO8 | ADS1299 RESET | ADS_RESET_N | Output |
| GPIO9 | ADS1299 DRDY | ADS_DRDY_N | Input, interrupt |
| GPIO10 | ADS1299 CS | ADS_CS_N | Output, SPI CS |
| GPIO11 | SPI MOSI | SPI_MOSI | SPI2 |
| GPIO12 | SPI SCLK | SPI_SCLK | SPI2 |
| GPIO13 | SPI MISO | SPI_MISO | SPI2 |
| GPIO15 | Buzzer drive | BUZ_DRV | Output, to Q1 base |
| GPIO16 | DRV2605L EN | HAPTIC_EN | Output |
| GPIO17 | DRV2605L IN | HAPTIC_IN | Output (trigger mode) |
| GPIO18 | MPU-6050 INT | IMU_INT | Input, interrupt |
| GPIO2 | Status LED | LED_STATUS | Output, onboard LED via 330 Ω |
| GPIO1 (TX) | UART TX | UART_TX | Debug UART, to J13 |
| GPIO0 (RX) | UART RX | UART_RX | Debug UART, to J13 |
| GPIO3 | Boot mode | BOOT_BTN | → SW1 → GND (same as IO0) |

**Debug header J13 (4-pin 2.54 mm):**
- Pin 1: GND
- Pin 2: 3V3
- Pin 3: UART_TX (GPIO1)
- Pin 4: UART_RX (GPIO0)

---

## 6. MPU-6050 IMU (U3)

**Power:**
- VDD → 3V3 + 100 nF + 10 µF decoupling to GND.
- VLOGIC → 3V3 + 100 nF decoupling to GND.
- GND → DGND.

**I2C:**
- SCL → I2C_SCL (with 4.7 kΩ pull-up to 3V3 shared with DRV2605L, one shared pull-up set is sufficient).
- SDA → I2C_SDA.
- AD0 → GND (sets I2C address 0x68; this is different from DRV2605L address 0x5A — no conflict).

**Interrupts and clocking:**
- INT → IMU_INT (GPIO18 on ESP32-S3). Add 100 Ω series resistor R_IMINT.
- FSYNC → GND (frame sync not used).
- CLKIN → GND or NC (uses internal oscillator).
- CPOUT → 100 nF to GND (charge pump bypass).

**Orientation:** Mount MPU-6050 with X-axis pointing toward the patient's right, Y-axis pointing up, Z-axis pointing anteriorly (out of the enclosure face). Mark orientation with silkscreen arrow.

---

## 7. DRV2605L HAPTIC DRIVER (U4)

**Power:**
- VDD → 3V3 + 100 nF + 10 µF decoupling to GND. Place within 1 mm.
- GND → DGND.

**I2C:**
- SCL → I2C_SCL.
- SDA → I2C_SDA.
- I2C address is 0x5A (fixed, no address pin).

**Control:**
- EN → HAPTIC_EN (GPIO16). Active HIGH enables device. Add 100 kΩ pull-down to GND so device starts disabled.
- IN/TRIG → HAPTIC_IN (GPIO17). In ERM/LRA external trigger mode (Mode=3), rising edge triggers playback.

**LRA output:**
- OUT+ → J11 pin 1 (LRA motor positive).
- OUT- → J11 pin 2 (LRA motor negative).
- Add 10 µF ceramic between OUT+ and OUT- as snubber (across the LRA terminals on PCB side).
- The LRA is a 10 × 3 mm 235 Hz linear resonant actuator connected via J11.

---

## 8. BUZZER DRIVE CIRCUIT

A self-oscillating active piezo buzzer requires only DC power gated by a transistor.

**Circuit:**
- 3V3 → BZ1 pin 1 (buzzer positive).
- BZ1 pin 2 (buzzer negative) → Q1 Collector (FMMT617, U7, NPN SOT-23).
- Q1 Emitter → GND.
- Q1 Base → R_BASE (1 kΩ, 0402) → BUZ_DRV (GPIO15 on ESP32-S3).
- R_BASE also has R_PULLDOWN (10 kΩ, 0402) from Base to GND to prevent floating base.
- Flyback diode D_BUZ (1N4148W SOD-123, anode=Collector, cathode=3V3) across buzzer for inductive spike protection.
- When GPIO15 = HIGH → Q1 turns on → buzzer activates (90 dB chirp).
- BZ1 is through-hole 12 mm piezo buzzer, height < 12 mm to fit within 20 mm enclosure depth.

---

## 9. USB-C CHARGING INPUT (J1)

Use a USB Type-C 16-pin SMD receptacle.

**Connections:**
- VBUS pins (CC1 and CC2) → 5.1 kΩ resistors R_CC1 and R_CC2 each to GND. This configures the device as a USB power sink, requesting 5V from any USB-C charger or USB-A adapter with USB-C cable.
- VBUS power pins → 10 µF + 100 nF decoupling to GND → TP4056 VIN.
- GND pins → GND.
- D+, D-, SBU1, SBU2 → NC (no data communication needed).

---

## 10. TEST POINTS

Place the following through-hole or SMD test pads (1 mm circle) for lab bring-up:

| Label | Net | Location |
|-------|-----|----------|
| TP_3V3 | 3V3 power rail | Near LDO U6 output |
| TP_VBAT | VBAT_SW | Near J10 battery connector |
| TP_AVDD | AVDD_FILT | Analog domain |
| TP_AGND | AGND | Near AGND-DGND star point |
| TP_DGND | DGND | Near U2 |
| TP_MOSI | SPI_MOSI | Near ADS1299 SPI |
| TP_MISO | SPI_MISO | |
| TP_SCLK | SPI_SCLK | |
| TP_DRDY | ADS_DRDY_N | |
| TP_SDA | I2C_SDA | Near U3/U4 |
| TP_SCL | I2C_SCL | |
| TP_GPIO1–4 | ADS1299 GPIO1–4 | Near U1 |

---

## 11. PCB LAYOUT RULES (CRITICAL — FOLLOW EXACTLY)

### 11.1 Component Placement

Divide the board into three distinct zones:

**Zone A — Analog Front-End (left 40% of board, ~34 mm wide):**
- Place ADS1299 (U1) centred in this zone.
- Place all 8 differential EMG input connectors J2–J9 along the left and top edges for short lead routing.
- Place BIAS electrode header J_BIAS adjacent to J2.
- Place all input protection resistors (R_PROTxP, R_PROTxN), differential caps (C_DIFFx), and CM bypass caps (C_CMx) as close as possible to ADS1299 input pins — within 2 mm.
- Place all ADS1299 bypass caps (C_AV1–C_AV4, C_DV1, C_DV2, C_VCAP, C_REF1, C_REF2) within 1 mm of their respective ADS1299 pins.
- Flood Zone A top copper with AGND pour. Connect to AGND net. No DGND in this zone except at the star-point resistor location.
- Route no digital signals through Zone A. SPI traces must enter ADS1299 from the right side (Zone B border) only.

**Zone B — Digital Processing (centre-right 45% of board, ~38 mm wide):**
- Place ESP32-S3 module U2 in the upper-right area. Orient module so PCB antenna faces the right or top edge with no copper underneath.
- Place MPU-6050 (U3) below U2.
- Place DRV2605L (U4) adjacent to U3.
- Place buzzer transistor U7 near GPIO15 route.
- Route all SPI and I2C traces within this zone.
- Bottom copper: solid DGND pour.

**Zone C — Power Management (bottom strip, ~15 mm tall):**
- Place TP4056 (U5) near USB-C connector J1.
- Place AP2112K LDO (U6) between U5 and Zone B.
- Place SW2 (battery disconnect) near J10 (battery JST).
- Place SW1 (boot/power button) accessible from enclosure edge.
- USB-C J1 on bottom-left edge.
- LiPo JST J10 on bottom-right edge.
- LRA JST J11 adjacent to DRV2605L.

### 11.2 Trace Widths

| Signal type | Width |
|-------------|-------|
| Power (3V3, VBAT) | 0.5 mm |
| LDO output (3V3 main) | 0.5 mm |
| AVDD_FILT | 0.4 mm |
| SPI traces (SCLK, MOSI, MISO, CS) | 0.2 mm |
| I2C traces (SDA, SCL) | 0.2 mm |
| ADS1299 control (DRDY, RESET, START, PWDN) | 0.2 mm |
| EMG electrode differential pair (INxP, INxN) | 0.15 mm |
| BIAS_ELEC trace | 0.15 mm |
| OUT+ / OUT- (LRA haptic) | 0.3 mm |
| USB VBUS power | 0.5 mm |
| GND fills | solid pour |

### 11.3 EMG Differential Trace Rules

- Each INxP / INxN pair must be routed as a **matched-length differential pair**. Maximum length mismatch: 0.5 mm.
- Route differential pairs with 0.15 mm gap between the two traces, 0.15 mm clearance from any other net.
- Do NOT route any digital signal parallel to and within 3 mm of any EMG differential pair.
- Differential pairs must run entirely over the AGND zone A copper pour on the bottom layer.
- No vias on EMG signal traces between electrode connector and ADS1299 pin. Route entirely on TOP layer within Zone A.
- Place guard trace rings (AGND-connected, 0.15 mm trace) around each differential pair group from connector to ADS1299.

### 11.4 SPI Trace Rules

- Maximum SPI trace length: 40 mm.
- All four SPI traces (SCLK, MOSI, MISO, CS_N) must be length-matched to within 2 mm of each other.
- Route SPI traces on TOP layer, away from EMG Zone A.
- Do not route SPI traces through Zone A.
- Place 33 Ω series termination resistors at source (ESP32-S3 GPIO pads), within 3 mm of pad.

### 11.5 I2C

- Route SDA and SCL together, 0.2 mm, on TOP layer.
- 4.7 kΩ pull-ups for both SDA and SCL at a single location near the midpoint between U2, U3, and U4.
- Maximum I2C bus length: 50 mm.

### 11.6 Power Trace Routing

- 3V3 main power: 0.5 mm trace from LDO output, branch to each subsystem with local decoupling caps at every IC VDD pin.
- Do NOT run power traces under ADS1299 body.
- AVDD_FILT: dedicate a separate 0.4 mm trace from ferrite bead L1 to ADS1299 AVDD pins only. Do not share with any other supply.

### 11.7 Ground Planes

- Bottom layer: 100% DGND copper pour with thermal reliefs on through-hole component pads only.
- Top layer Zone A: AGND copper pour.
- AGND and DGND single-point connection: 0 Ω resistor R_GND (0402) at one location only, placed directly adjacent to ADS1299 AVSS pins.
- Add stitching vias (0.3 mm drill, 0.6 mm pad) every 5 mm around board perimeter and around Zone A/B boundary to stitch TOP pours to BOTTOM DGND.

### 11.8 Clearances

- USB-C VBUS traces: 0.5 mm clearance minimum from all signal traces.
- LRA OUT+ / OUT-: 0.3 mm clearance from signal traces.
- Battery VBAT: 0.5 mm clearance from USB-C traces.
- EMG differential pairs: 0.3 mm clearance from all other nets (except guard ring).

---

## 12. DECOUPLING CAPACITOR SUMMARY

Place ALL decoupling caps as close as possible to the pin they decouple. Use 0402 SMD ceramic X5R or X7R dielectric.

| Ref | Value | Dielectric | Location |
|-----|-------|------------|----------|
| C_AV1 | 10 µF | X5R | AVDD_FILT to AGND |
| C_AV2 | 1 µF | X7R | AVDD_FILT to AGND |
| C_AV3 | 100 nF | X7R | AVDD_FILT to AGND |
| C_AV4 | 10 nF | X7R | AVDD_FILT to AGND |
| C_DV1 | 10 µF | X5R | ADS1299 DVDD to DGND |
| C_DV2 | 100 nF | X7R | ADS1299 DVDD to DGND |
| C_VCAP | 10 µF | X5R | ADS1299 VCAP to AGND |
| C_REF1 | 10 µF | X5R | ADS1299 VREFP to AGND |
| C_REF2 | 100 nF | X7R | ADS1299 VREFP to AGND |
| C_VIN_TP | 10 µF | X5R | TP4056 VIN to GND |
| C_VIN_TP2 | 100 nF | X7R | TP4056 VIN to GND |
| C_LDO_IN1 | 10 µF | X5R | LDO VIN (VBAT_SW) |
| C_LDO_IN2 | 1 µF | X7R | LDO VIN |
| C_LDO_OUT1 | 10 µF | X5R | LDO 3V3 output |
| C_LDO_OUT2 | 100 nF | X7R | LDO 3V3 output |
| C_ESP_BULK | 100 µF | Electrolytic 1206 | ESP32 3V3 supply |
| C_ESP1 | 10 µF | X5R | ESP32 VDD |
| C_ESP2 | 100 nF | X7R | ESP32 VDD |
| C_MPU1 | 10 µF | X5R | MPU-6050 VDD |
| C_MPU2 | 100 nF | X7R | MPU-6050 VDD |
| C_MPU3 | 100 nF | X7R | MPU-6050 VLOGIC |
| C_MPU4 | 100 nF | X7R | MPU-6050 CPOUT |
| C_DRV1 | 10 µF | X5R | DRV2605L VDD |
| C_DRV2 | 100 nF | X7R | DRV2605L VDD |
| C_LRA | 10 µF | X5R | LRA OUT+ to OUT- (across motor) |
| C_BIASREF | 100 nF | X7R | ADS1299 BIASREF to AGND |
| C_CMx_P/N | 10 nF × 16 | X7R | Each INxP and INxN to AGND (16 total) |
| C_DIFFx | 47 pF × 8 | C0G | Differential, across each INxP–INxN pair (8 total) |

---

## 13. SILKSCREEN AND MARKINGS

Add clear silkscreen labels for all connectors:

- J2: "L_TA+ / L_TA-" (Left Tibialis Anterior)
- J3: "L_GM+ / L_GM-" (Left Gastrocnemius)
- J4: "L_VL+ / L_VL-" (Left Vastus Lat.)
- J5: "L_BF+ / L_BF-" (Left Biceps Femoris)
- J6: "R_TA+ / R_TA-" (Right Tibialis Anterior)
- J7: "R_GM+ / R_GM-" (Right Gastrocnemius)
- J8: "R_VL+ / L_VL-" (Right Vastus Lat.)
- J9: "R_BF+ / R_BF-" (Right Biceps Femoris)
- J_BIAS: "BIAS ELECTRODE (Patella)"
- J1: "USB-C CHARGE 5V"
- J10: "LIPO 3.7V"
- J11: "LRA HAPTIC"
- J12: "BUZZER"
- J13: "DEBUG UART GND/3V3/TX/RX"
- SW1: "BOOT"
- SW2: "BATTERY"

Add version text on silkscreen: "WalkInPeace v1.0 | U-18 | 2-LAYER | JLCPCB"

Add safety note: "BATTERY POWERED — NO MAINS CONNECTION" in silkscreen on bottom layer.

Mark AGND/DGND star-point location with silkscreen cross-hair.

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## 14. FABRICATION OUTPUT REQUIREMENTS

Generate the following outputs:

1. **Gerber files** (RS-274X): Top copper, Bottom copper, Top solder mask, Bottom solder mask, Top silkscreen, Bottom silkscreen, Board outline (Edge.Cuts), Drill file (Excellon).
2. **BOM** (CSV): Reference designator, value, part number, quantity, footprint.
3. **Pick-and-place file** (CSV): X/Y centroid, rotation, layer for all SMD components.
4. **Schematic PDF** (A3): All sheets, full netlist visible.
5. **3D render** (STEP or PNG): Top view and isometric.

Target PCB house: **JLCPCB** (Standard 2-layer, ENIG, green solder mask, 5 PCBs per order, delivery to Singapore).

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## 15. DESIGN RULES CHECK (DRC) — MUST PASS ALL

Before finalising, confirm all of the following pass with zero errors:

- [ ] No trace width below 0.15 mm
- [ ] No clearance violation below 0.15 mm
- [ ] No unconnected nets (zero airwires)
- [ ] AGND and DGND connected at exactly one point (R_GND star point)
- [ ] EMG differential pairs length-matched within 0.5 mm
- [ ] No copper in ESP32-S3 antenna keep-out zone
- [ ] All bypass capacitors placed within 1 mm of their target IC pin
- [ ] No digital signal traces in Zone A analog region
- [ ] USB-C CC1/CC2 resistors 5.1 kΩ present
- [ ] ADS1299 CLKSEL tied high (internal oscillator)
- [ ] ADS1299 PWDN, RESET pull-ups to 3V3 present
- [ ] ADS1299 DVDD not externally driven (caps only)
- [ ] Ferrite bead L1 present between 3V3 and AVDD_FILT
- [ ] All 8 differential channel pairs connected to ADS1299 input pins
- [ ] BIAS circuit present: BIASOUT → R_BIAS 10 kΩ → J_BIAS header
- [ ] Board dimensions within 85 mm × 55 mm

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*End of WalkInPeace Flux.ai PCB Design Prompt v1.0*
*Project Code: U-18 | Engineering Innovation Challenge 2026*
*NTU School of Chemistry, Chemical Engineering and Biotechnology / LKCMedicine*