Design an editable schematic for a Gigabit Ethernet interface between a
TI AM62L System-on-Module and an external PHY. Use real parts. After drafting,
run ERC. Keep RGMII as a matched group and MDI as 100-ohm differential pairs.

PARTS
- U1  AM62L STAMP SOM (Calixto)   — use CPSW3G port 1 (RGMII1) + MDIO0 + IO power
- U2  Ethernet PHY  = TI DP83867IRPAP (RGMII, Gigabit)
- J1  RJ45 with integrated 10/100/1000 magnetics (MagJack) + link/act LEDs
      (or discrete magnetics T1 + plain RJ45)
- Y1  25.000 MHz crystal + 2 load caps (value per PHY CL, ~18-22 pF typ)
- Passives: strap resistors, MDIO pull-up, reset RC, decoupling, MDI terminations

POWER
- VDDIO(PHY) MUST equal the SOM RGMII1 IO voltage (set both to 1.8 V)
- PHY core (1.0 V) from PHY internal regulator (or external), AVDD analog rail
- Decoupling per DP83867 datasheet on every rail

NET LIST  (SOM signal  <->  PHY signal)
# RGMII data/clock (12 nets)
RGMII_TXC     : U1.RGMII1_TXC     <-> U2.GTX_CLK
RGMII_TX_CTL  : U1.RGMII1_TX_CTL  <-> U2.TX_CTRL
RGMII_TXD0    : U1.RGMII1_TD0     <-> U2.TX_D0
RGMII_TXD1    : U1.RGMII1_TD1     <-> U2.TX_D1
RGMII_TXD2    : U1.RGMII1_TD2     <-> U2.TX_D2
RGMII_TXD3    : U1.RGMII1_TD3     <-> U2.TX_D3
RGMII_RXC     : U2.RX_CLK         <-> U1.RGMII1_RXC
RGMII_RX_CTL  : U2.RX_CTRL        <-> U1.RGMII1_RX_CTL
RGMII_RXD0    : U2.RX_D0          <-> U1.RGMII1_RD0
RGMII_RXD1    : U2.RX_D1          <-> U1.RGMII1_RD1
RGMII_RXD2    : U2.RX_D2          <-> U1.RGMII1_RD2
RGMII_RXD3    : U2.RX_D3          <-> U1.RGMII1_RD3
# Place 0-ohm series resistor footprints on TXC and RXC for SI tuning

# Management bus
MDIO : U1.MDIO0_MDIO <-> U2.MDIO   ; add 2.2k pull-up to VDDIO
MDC  : U1.MDIO0_MDC  <-> U2.MDC

# Reference clock
U2.XI <-> Y1 pin1 ; U2.XO <-> Y1 pin2 ; load caps Y1->GND both pins

# Reset & interrupt
PHY_RSTn : U2.RESET_N <- reset RC (10k to VDDIO + 100nF to GND) ; also to U1 GPIO
PHY_INTn : U2.INT_PWDN_N -> U1 GPIO ; 4.7k pull-up to VDDIO

# Straps (DP83867 samples at reset rising edge)
Set via pull-up/pull-down resistors on the strap pins per the DP83867
strap table: PHY address, RGMII delay/mode, auto-negotiation.
NOTE: LED_0/LED_1 and some RX pins double as straps — the LED and pull
resistors must not conflict with the intended strap value.

# RGMII delay — pick ONE (do not delay both sides)
Use PHY internal delay (set delay strap) OR MAC internal delay.
Must match the Linux device-tree phy-mode (rgmii-id / rgmii-rxid / rgmii-txid).

# MDI pairs + line side
MDI_0+/-, MDI_1+/-, MDI_2+/-, MDI_3+/- : U2 -> magnetics primary (100-ohm diff)
Magnetics secondary -> J1 RJ45 pairs
Centre-tap caps to GND; Bob-Smith termination (75-ohm to common + 1nF/2kV to chassis)
RJ45 shield to chassis via 1M + 1nF; PHY LED_0/LED_1 -> J1 link/activity LEDs