CAT DETERRENT SPRAYER — FINAL FLUX BOARD REPAIR
Use this on the EXISTING project. Goal: minimum changes, minimum AI/Auto-Layout cost.

IMPORTANT
Do NOT redesign the board.
Do NOT change the 34 mm circular outline, Standard 2 Layer stackup, mounting holes, external connector locations, U1, U2, Q1, D1, or existing good traces.
Do NOT work on firmware, enclosure, PIR range, cosmetics, or component substitutions unless specifically requested below.
Do NOT launch or rerun Auto-Layout from Chat. Complete the preparation below, then STOP and report:
READY FOR ONE AUTO-LAYOUT JOB

CURRENT PROJECT FACTS
Board: 34 mm circular, Standard 2 Layer.
Existing routed nets include the pump drive, 5 V rails, 3.3 V rail, LED control, PIR signal and pump gate.
Nets with no explicit routed trace segments in the current export:
- KA_EN_ISP_SCK
- LED_STAT_ANODE
- POT_WIPER_ISP_MISO
- RESET
- KA_LOAD_SW
GND has no explicit traces because Flux can use copper fills; do not assume GND is broken only because it has no trace segments.

MAKE ONLY THESE CHANGES

1. F1 MUST BE POPULATED
F1 is currently incorrectly Exclude from BOM = true.
Change F1 Exclude from BOM to FALSE.
Keep F1 = Littelfuse 1812L110/33MR, 1.1 A hold PPTC.
If editable, correct:
Manufacturer Name = Littelfuse
Manufacturer Part Number = 1812L110/33MR
Do not remove, bypass, or mark F1 optional.

2. ADD R6 TO PROTECT ISP MISO
Add one 1 kΩ 0603 resistor, reference R6.
Change only the RV1 wiper connection as follows:
RV1 pin 2 -> new net POT_WIPER_RAW -> R6 -> existing POT_WIPER_ISP_MISO.
The existing POT_WIPER_ISP_MISO side must still connect directly to:
- U1 PB1/MISO
- J4 MISO
Do NOT put R6 between U1 and J4.
Keep:
RV1 pin 3 -> 3V3_LOGIC
RV1 pin 1 -> GND

3. MOVE C4 NEXT TO U2
C4 is the MCP1700 1 µF output capacitor and is presently too far from U2.
Move C4 physically adjacent to U2 VOUT/GND with the shortest practical connection.
Prefer the same side as U2 if space permits.
Do NOT move U2.
Do NOT change C4 value or footprint.
Only remove/replace the old C4 trace branch if moving C4 requires it.

4. C6 POLARITY / BOM CLARITY
Keep C6 = 220 µF, 10 V, existing CP_Elec_6.3x5.4 footprint.
Treat it as a POLARIZED electrolytic:
C6 pad 1 / + -> VBUS_5V
C6 pad 2 / - -> GND
Do not swap these nets.
If possible, correct its Part Type from generic non-polarized capacitor to polarized electrolytic and ensure the PCB polarity mark is clear.
Do not replace the footprint merely to change metadata.

5. GND
Flux ground fills are normally enabled automatically.
Verify the GND copper fill is active on both Top and Bottom.
If it is already active, make NO change.
Do not manually route every GND pad.
Do not add a stitching-via grid unless a real DRC floating-copper/GND problem requires it.

6. KEEP EXISTING POWER ROUTING
Do NOT globally widen or reroute VBUS_IN_RAW, VBUS_5V, PUMP_SW or PUMP_GATE.
The existing export already has wider traces on the main pump/power path and narrower branches where appropriate.
Preserve those routes unless a real DRC violation requires a local correction.

7. KEEP THESE OPTIONAL / DNP
Leave these optional/excluded as they currently are:
D2, Q2, R5, J4, TP1, TP2, TP3, TP4, TP5, TP6.
Do not spend time changing D2 metadata.
Do not add a pump-disable jumper.
During ISP programming the pump will simply be unplugged from J2.

8. PRESERVE ALL OTHER WORKING CIRCUIT CHOICES
Keep:
U1 ATtiny85
U2 MCP1700-3.3
Q1 AO3400A
D1 MBR230 flyback diode
R1/R2 pump-gate network
J1 power input
J2 pump connector
J3 PIR connector
J4 ISP function
34 mm round board
H1-H4 mounting holes
Standard 2 Layer stackup

AFTER THESE EDITS
Do not try multiple routing attempts in Chat.
Check the live DRC/messages and fix only errors caused directly by the edits above.
Then STOP and say exactly:
READY FOR ONE AUTO-LAYOUT JOB

ONE AUTO-LAYOUT JOB — USER WILL START THIS MANUALLY
When Auto-Layout is started, preserve all existing committed traces/vias and route the remaining airwires only.
The remaining work should mainly be:
- KA_EN_ISP_SCK
- RESET
- LED_STAT_ANODE
- KA_LOAD_SW
- R6 / POT_WIPER_RAW
- POT_WIPER_ISP_MISO as changed by R6
- C4 connections after its move
- any genuine remaining airwire reported by Flux DRC

Do not require full convergence if an available iteration already has:
- zero airwires
- no overlapping traces/shorts
- no missing required footprints
- no invalid-layer errors
- no floating copper
Apply the first clean satisfactory iteration.

FINAL ACCEPTANCE CHECK
Do not call the board finished unless all are true:
- F1 Exclude from BOM = FALSE.
- R6 = 1 kΩ is only between RV1 wiper and the U1/J4 MISO node.
- C4 is adjacent to U2.
- C6 polarity is pad 1/+ to VBUS_5V and pad 2/- to GND.
- GND fill works on both copper layers.
- Existing pump/power routes were preserved unless a DRC-required local fix was necessary.
- Zero airwires remain.
- No shorts/overlapping different nets.
- No missing required footprints.
- No invalid layers.
- No floating copper.
- Board remains 34 mm circular, 2-layer, with H1-H4 and external connectors unchanged.

IF ANY ITEM CANNOT BE COMPLETED
Do not improvise, redesign, or repeatedly retry.
State the exact unresolved item and stop so the project can be reviewed externally.