# ATLAS X — Flux Master Execution Prompt Copy the complete prompt below into the **existing Agent thread** of the existing Flux project `ATLAS X Control Board – Revision A`. Do not create a new project. --- ## MASTER PROMPT Resume and complete the existing Flux project **“ATLAS X Control Board – Revision A”**. Work in the existing project and existing Agent thread. Do not fork, recreate, or replace the project with a new design. This prompt is the new authoritative specification. It supersedes every earlier project brief, project description, Agent instruction, and preliminary circuit that conflicts with it. In particular, the current public project description is obsolete where it still includes a populated OLED, three populated buttons, future fan labels, no HP power control, or GPIO7 as spare. Do not merely propose changes. Apply the changes to the schematic, component data, PCB layout, project documentation, and 3D board representation. Continue through all phases without asking the user to confirm ordinary implementation choices. Stop only if a required Flux action is technically impossible, a primary-source datasheet is unavailable, or exact physical information would otherwise have to be invented. If blocked, preserve all completed work and report the exact blocker and last completed phase. ### 1. Product definition and fixed architecture ATLAS X is a separate intelligent computer used beside a MacBook Air M1. It contains: - an HP 250 G6 motherboard used as a headless Windows/Linux compute node; - Intel Core i5-7200U, Radeon 520, 8 GB RAM, and Samsung M.2 SATA 256 GB as the currently identified HP configuration; - the original HP heatsink and fan; - no HP battery in Revision A; - an ATLAS control PCB with a removable ESP32-S3 DevKit; - a self-powered internal USB 3 hub; - a USB-to-Gigabit-Ethernet adapter and a direct Ethernet link to the HP; - one external certified low-voltage DC supply, with HP power and an isolated 5 V logic branch handled outside this control PCB; - ATLAS Core local-AI software on the HP, ATLAS Sentinel firmware on the ESP32, and the ATLAS app on the Mac. The Mac connects to ATLAS X through one USB-C cable for data only. The Mac must not be charged or back-fed by ATLAS X. The control PCB carries no USB 3, Ethernet, HP operating power, CPU, RAM, GPU, SSD, battery, charger, display, keyboard, touchpad, or other HP internal buses. The only intentional HP interactions with the control PCB are: 1. an isolated dry-contact output wired in parallel with the two verified contacts of the original HP momentary power switch; 2. a non-contact optical pickup placed over the original HP power LED; 3. a separate DS18B20 temperature probe placed inside the enclosure. Ethernet, HP DC input, the original HP fan, and every HP data connection bypass the control PCB. ### 2. Controller and authoritative GPIO map Use the official removable **Espressif ESP32-S3-DevKitC-1-N8R8, hardware revision v1.1**, installed on two correctly spaced 1 x 22 female socket headers. Verify the footprint, header spacing, pin numbering, board outline, antenna location, button locations, and both Micro-USB connector positions against Espressif primary-source files before placement. Official reference: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitc-1/user_guide_v1.1.html Important facts: - v1.1 has two Micro-USB ports, not USB-C; - the internal hub normally connects to the USB-to-UART Micro-USB port for power and serial data; - both Micro-USB ports, BOOT, and RESET must remain accessible; - the carrier must not inject 5 V or 3.3 V into the DevKit and must not add another USB connector; - the carrier may use the DevKit 3.3 V output only for its low-power logic and sensors; - GPIO38 drives the onboard RGB LED; - GPIO35, GPIO36, and GPIO37 are unavailable on the N8R8 configuration; - GPIO19 and GPIO20 are reserved for native USB and must remain unconnected on the carrier; - GPIO43 and GPIO44 are reserved for service/UART; - GPIO0, GPIO3, GPIO45, and GPIO46 are boot/strapping-sensitive and must not be used or exposed as ordinary expansion pins. Use this final map and the official v1.1 J1 header pin numbers: | DevKit signal | Official J1 position | ATLAS net/function | Rule | |---|---:|---|---| | GPIO4 | J1 pin 4 | `HP_STATE_IN` | active high after optical-state conditioning | | GPIO5 | J1 pin 5 | `FUTURE_KEY_1` | DNP future header only | | GPIO6 | J1 pin 6 | `FUTURE_KEY_2` | DNP future header only | | GPIO7 | J1 pin 7 | `HP_PWR_CTRL` | active high, 100 kOhm pull-down, safe LOW at reset | | GPIO15 | J1 pin 8 | `STATUS_LED` | internal service LED | | GPIO16 | J1 pin 9 | `TEMP_1W` | DS18B20 data | | GPIO17 | J1 pin 10 | `EXP_GPIO17` | DNP future expansion only | | GPIO18 | J1 pin 11 | `EXP_GPIO18` | DNP future expansion only | | GPIO8 | J1 pin 12 | `FUTURE_I2C_SDA` | DNP future I2C header | | GPIO9 | J1 pin 15 | `FUTURE_I2C_SCL` | DNP future I2C header | | GPIO10 | J1 pin 16 | `FUTURE_KEY_3` | DNP future header only | Mark every unused DevKit pin explicitly no-connect where appropriate. Connect the available DevKit ground pins to the control-domain ground plane. Do not connect J1 5 V to the carrier power network. ### 3. Replace the old user-interface circuitry Revision A has **no populated display, no populated user buttons, and no external front panel**. - Delete `SW1`, `SW2`, `SW3`, their obsolete debounce network, the old OLED module, and the two old OLED mechanical mounting holes. - Remove obsolete fan names and fan functions. GPIO17 and GPIO18 are generic future expansion only; there is no fan driver, tachometer circuit, fan-power connector, or fan supply on this PCB. - Investigate the current `R7` and `R8`. If they do not have a necessary, unambiguous role in the new approved circuits, delete them. No unexplained or orphan component may remain. - Re-annotate only as needed and report the final reference mapping. Keep these DNP future provisions: - `J_FUTURE_I2C`: unpopulated 1 x 4, 2.54 mm header, pins `GND`, `3V3`, `GPIO8/SDA`, `GPIO9/SCL`; - optional 4.7 kOhm I2C pull-up footprints, both DNP by default; - `J_FUTURE_KEYS`: unpopulated 1 x 4, 2.54 mm header, pins `GND`, `GPIO5`, `GPIO6`, `GPIO10`, with safe pull-ups and clearly documented active-low use; - `J_EXP`: unpopulated header containing `GND`, `3V3`, `GPIO17`, and `GPIO18`, labelled `3V3 LOGIC ONLY — NOT 5V TOLERANT`. No DNP header may be interpreted by firmware as an HP power control. ### 4. Isolated HP power-button interface Create a dedicated schematic block named `HP POWER CONTROL — ISOLATED`. #### 4.1 Hardware-bounded command path Implement the final safety gate using: - preferred timer: Analog Devices `LTC6993-1`, non-retriggerable, rising-edge one-shot, operated at 3.3 V with a positive active pulse; - preferred gate: Texas Instruments `SN74LVC1G08`, single two-input AND gate, operated at 3.3 V; - one 100 nF local decoupling capacitor at each logic IC; - a 100 kOhm, 1% pull-down directly on raw `HP_PWR_CTRL` / GPIO7. Use `HP_PWR_CTRL` as both the one-shot trigger and one input to the AND gate. Use the one-shot output as the second AND input. Name the AND output `HP_PWR_GATE`. Configure the LTC6993-1 for a nominal hardware window of approximately **7.1 seconds**. The preferred starting calculation is `NDIV = 2^21` and `RSET = 169 kOhm, 1%`, but verify the complete DIV network, output polarity, exact orderable suffix, pinout, formula, tolerance, and power-up behavior against the current Analog Devices datasheet. Document the calculation. The verified worst-case window, including IC error and resistor tolerance, must be longer than 6.2 s and shorter than 7.8 s. Do not substitute a retriggerable timer unless additional hardware provably enforces the same continuous-on limit. Official reference: https://www.analog.com/media/en/technical-documentation/data-sheets/ltc6993-6993-1-6993-2-6993-3-6993-4.pdf Required behavior: - a 500 ms GPIO7 high command produces one approximately 500 ms `HP_PWR_GATE` pulse; - a deliberate 6 s GPIO7 high command produces one approximately 6 s pulse; - GPIO7 stuck high is cut off by hardware before 8 s; - the circuit does not retrigger until GPIO7 returns low and a new rising edge occurs; - power-up, brownout, reset, USB connection, firmware download, and timer start-up produce no false PhotoMOS activation. #### 4.2 PhotoMOS and isolated output Use one genuine Panasonic `AQY212EH`, normally-open 1 Form A PhotoMOS in the official through-hole DIP-4 package. Verify pin numbers, input polarity, output terminals, package dimensions, isolation rating, LED drive requirements, and footprint from the current Panasonic datasheet. Official reference: https://industry.panasonic.com/ac/e_download/control/relay/photomos/catalog/semi_eng_ge1a_aqy21_e.pdf - Drive the PhotoMOS input LED anode from `HP_PWR_GATE` through a calculated 1% resistor, at least 0.125 W. Do not blindly preserve the old 470 Ohm value. Calculate from the guaranteed `SN74LVC1G08` VOH and the Panasonic maximum LED forward voltage so the worst-case current remains above the PhotoMOS maximum operate current with engineering margin, while the nominal current is approximately 5-8 mA and always remains below the Panasonic input limit. A value near 249-330 Ohm is a starting range only; the verified calculation determines the final value. - Connect the PhotoMOS input LED cathode only to control-domain GND. - Connect the two PhotoMOS output terminals only to `HP_PWR_SW_A` and `HP_PWR_SW_B`. - Terminate those nets at `J_HP_PWR_SW`, using JST `B2B-XH-A(LF)(SN)`. - Add the mating `XHP-2` housing and `SXH-001T-P0.6` contacts to the system/harness BOM. - The two output nets have no required polarity. - The HP-side cable is named `TBD-HARNESS`; do not invent an HP ribbon connector or pinout. Create an `HP_ISOLATED` net class and a visible no-copper isolation corridor. No plane, pour, trace, test point, resistor, ESD part, or unrelated component may bridge the PhotoMOS boundary. Place the PhotoMOS and `J_HP_PWR_SW` together at one board edge, with the output-side traces short and completely inside the isolated zone. Add silkscreen: `HP POWER SW — ISOLATED — DRY CONTACT ONLY` Add this assembly note verbatim: `Connect only in parallel with the two contacts of the original HP momentary power switch after the contact pair passes three identical unpowered continuity tests. Never connect this output to the HP charger, battery, motherboard power rails, or an unverified ribbon connector.` ### 5. Galvanically isolated HP state detection by optical pickup Finalize Revision A with a non-contact optical pickup rather than an electrical tap into the HP LED circuit. This choice removes the unknown HP LED voltage, polarity, and ribbon pinout from the PCB. Use a remote Vishay `TEPT4400` visible-light phototransistor mounted over the original HP power LED inside an opaque light shroud. The sensor is part of the system/harness BOM, not mounted on the main control PCB. Official reference: https://www.vishay.com/docs/81341/tept4400.pdf On the carrier: - add `J_HP_LIGHT`, JST `B2B-XH-A(LF)(SN)`, two pins; - pin 1: `HP_LIGHT_RAW`, connected to the verified TEPT4400 collector through the harness; - pin 2: `GND`, connected to the verified TEPT4400 emitter through the harness; - add a fixed 10 kOhm minimum pull-up plus a 100 kOhm adjustment trimmer wired fail-safe as a variable pull-up from 3V3 to `HP_LIGHT_RAW`; - add an RC low-pass suitable for rejecting short light noise without preventing the firmware's 100 ms stable-state requirement; - feed `HP_LIGHT_RAW` through a 3.3 V Schmitt-trigger inverter, preferred `SN74LVC1G14`, so `HP_STATE_IN` / GPIO4 is HIGH when the HP power LED is illuminated and LOW in darkness; - add 100 nF local decoupling at the Schmitt inverter; - add test points for `HP_LIGHT_RAW` and `HP_STATE_IN`. Verify the TEPT4400 lead identification and the selected trimmer footprint from primary datasheets. Use a real orderable trimmer with an accessible adjustment screw and a valid 3D model. The sensor connector and all control-side circuitry remain in the ESP32 domain. There must be no conductive path to the HP LED board; the only crossing is light. Document that firmware accepts an electrical-state change only after at least 100 ms of stability and that HP electrical state alone does not mean the OS is online. `ONLINE` requires both `HP_STATE_IN` and the ATLAS Core network heartbeat. ### 6. Temperature, indicators, and service points #### Temperature - Add `J_TEMP`, JST `B3B-XH-A(LF)(SN)`, pins in the clearly labelled order `GND`, `3V3`, `DATA`. - Use a three-wire, externally powered DS18B20 probe at 3.3 V; do not use parasite-power mode. - Connect `DATA` to GPIO16 as `TEMP_1W`. - Add the required 4.7 kOhm, 1% pull-up from `TEMP_1W` to 3V3. - Put the mating `XHP-3` housing and correct JST contacts in the system BOM. - Define the cable pinout by pin number, not by unverified wire colors. Official reference: https://www.analog.com/media/en/technical-documentation/data-sheets/ds18b20.pdf #### Indicators - `POWER`: internal 3 mm through-hole LED connected to the true 3.3 V rail through a calculated current-limiting resistor; nominal LED current about 1-2 mA. - `STATUS`: internal 3 mm through-hole LED controlled active-high by GPIO15 through a calculated current-limiting resistor; nominal LED current about 1-2 mA. - These are service indicators visible only when the case is open, not a front panel. #### Decoupling and test points - Add one appropriately sized local bulk capacitor on the carrier 3.3 V rail and 100 nF decoupling at every active logic IC. - Test points: `3V3`, at least two `GND`, raw `HP_PWR_CTRL`, `HP_PWR_GATE`, `HP_LIGHT_RAW`, `HP_STATE_IN`, `TEMP_1W`, `FUTURE_I2C_SDA`, and `FUTURE_I2C_SCL`. - Do not add a 5 V/VBUS test point or any alternate power-injection path. ### 7. Component selection and BOM rules - Use only real, currently orderable manufacturer part numbers from primary or authorized sources. - Use the exact Panasonic PhotoMOS and the exact Espressif DevKit variant; no generic substitutes. - Use 0805 passives where practical for inspection and hand rework; small safety/timing logic may be SMD and professionally assembled. - Use through-hole JST XH connectors, 3 mm LEDs, and the DIP-4 PhotoMOS. - Select two exact 1 x 22 female socket header MPNs with the verified DevKit spacing and insertion height. - Every populated component must have a verified symbol, pin mapping, footprint, courtyard, height, manufacturer part number, and valid 3D model. - If a trustworthy library item is incomplete, repair or create the component from the manufacturer datasheet before using it. Do not silently use a similar package. - Produce two separate tables: `PCB BOM` and `SYSTEM/HARNESS BOM`. - Mark future headers and optional I2C pull-ups explicitly `DNP — REV A`. - Do not include the powered USB hub, Ethernet adapter, isolated DC/DC converter, HP power branch, or AI accelerator electrically on this PCB. List them only as system-level modules whose exact selection remains outside this PCB design. ### 8. Schematic verification before layout Before changing PCB placement, complete and organize the schematic into readable functional blocks. Run ERC and a connectivity audit. Resolve every real error; do not hide errors with blanket exceptions. Required schematic checks: 1. official DevKit header mapping matches the v1.1 primary source; 2. no use of excluded GPIOs; 3. GPIO7 is LOW by passive hardware at reset; 4. timer/gate/PhotoMOS path has the required 500 ms, 6 s, and sub-8 s behavior; 5. no false power-button pulse at power-up or reset; 6. no conductive path from `HP_PWR_SW_A/B` to GND, 3V3, 5 V, USB, or any other carrier net; 7. optical state sensing has no HP electrical connection; 8. DS18B20 is in powered three-wire mode with the correct pull-up; 9. all IC power pins and decoupling are present; 10. no unexplained `R7`, `R8`, orphan net, unconnected required pin, duplicate net name, or obsolete OLED/button/fan circuit remains. Add a short FMEA focused on false HP power-button activation, GPIO stuck high, sensor disconnect, ambient-light leakage, USB loss, DevKit removal, and connector reversal. Implement any low-cost, in-scope improvement needed to make a dangerous failure fail OFF. Do not continue to layout unless the HP power-control isolation audit is `PASS` and the timing calculation is `PASS`. ### 9. PCB layout and routing After the schematic passes, complete placement and routing. - Two-layer FR-4, 1.6 mm, 1 oz copper. - Preferred exact outline: 90.0 x 70.0 mm. It may grow only if proven necessary, never beyond 100 x 80 mm; report and freeze the final dimensions. - Coordinate origin: lower-left corner of the finished board. - Four 3.2 mm NPTH M3 holes, preferably at `(5,5)`, `(85,5)`, `(5,65)`, `(85,65)` for a 90 x 70 mm outline. Move them only to resolve a verified collision and report every final coordinate. - Rounded corners, nominal 4 mm radius. - Place the DevKit so both Micro-USB connector faces are accessible at one board edge and its PCB antenna faces an outer edge. - Reproduce the complete Espressif antenna keep-out on both copper layers: no copper pour, trace, component, or unrelated metal in the prohibited volume. - Maintain top access to BOOT, RESET, the state-sensor trimmer, and every service test point. - Place JST connectors at edges with their insertion direction unobstructed. - Keep `J_HP_PWR_SW` and the PhotoMOS output side at the isolated edge and visibly separated from control-domain copper. - Use a continuous ground reference in the control domain only. Do not pour ground through the isolated PhotoMOS corridor or beneath the antenna keep-out. - Route all nets; zero airwires are allowed. - Use conservative manufacturable widths and clearances. There are no high-speed USB or Ethernet traces on this PCB. - Add unambiguous pin-1, polarity, voltage, DNP, and connector-function labels. - Silkscreen title: `ATLAS X — CONTROL REV A` plus the final board revision. - Add `NO HP POWER RAILS`, `3V3 LOGIC ONLY`, and the isolated dry-contact warning where legible. Run final DRC and resolve every true error. Check silkscreen-to-pad clearance, connector mating space, DevKit insertion/removal space, component courtyards, M3 washer clearances, cable bend direction, and maximum component heights. ### 10. 3D board model and mechanical handoff Create a mechanically useful assembled-board 3D view, not a decorative render. - The 3D view must show the installed ESP32-S3-DevKitC-1-N8R8 v1.1, both female headers, JST connectors, PhotoMOS, timer/gates, trimmer, LEDs, capacitors, and all other populated parts. - Correct any missing, rotated, offset, floating, or wrong-scale 3D component model. - DNP headers/components must be identified as unpopulated and must not falsely appear as installed in the Revision A assembly. - Perform a visual collision and accessibility check in 3D. - Create a mechanical handoff table with: exact board outline, thickness, corner radii, M3 hole coordinates, connector face coordinates and insertion directions, Micro-USB access envelopes, antenna keep-out envelope, trimmer access envelope, and maximum populated height above and below the PCB. - Prepare the project so the user can export the precise bare board as STEP and the populated assembly as STL or COLLADA using Flux's supported export functions. - If the Agent cannot invoke exports directly, do not claim that files were exported; give the exact manual export menu actions after completing the in-project 3D validation. Flux is responsible here for the exact **control-board** 3D model. Do not invent a full HP motherboard, heatsink, hub, DC/DC module, power harness, or enclosure geometry. Those items belong to the later FreeCAD system assembly and require measured outlines or verified STEP files. Create a document named `AX-3D-HANDOFF` listing every external model still needed and the connection/clearance interface to the control PCB. A placeholder may be used only if it is explicitly named `UNVERIFIED ENVELOPE — NOT FOR FIT TEST`, has no invented claim of accuracy, and is excluded from pass/fail collision results. The eventual full ATLAS X CAD assembly must include the real HP motherboard, original heatsink/fan, Samsung M.2 SATA SSD, original HP DC jack/board, original power-button/LED board, retained HP daughterboards, hub, Ethernet adapter, isolated DC/DC, protected power distribution, control PCB, cables, airflow, standoffs, removable panels, and a future accelerator bay. Do not model any of those from photographs alone. ### 11. Firmware and system notes to record in the project Add these requirements to the project documentation; do not add extra hardware for them: - Sentinel sets GPIO7 LOW before enabling normal application logic. - Normal start is one nominal 500 ms high command. - Emergency hold is one 6 s command, available only after the Mac app completes two separate confirmations and a `PREPARE` / `COMMIT` exchange. - No emergency hold is automatic and the AI cannot issue or confirm it. - No power pulse during boot, reset, USB connection, firmware recovery, network connection, or fault recovery. - HP readiness requires both the stable optical state input and ATLAS Core network heartbeat. - After a blackout, automatically restore ON only when persistent `desired_state = ON`, after self-test, and only if the HP is confirmed off. Make one attempt, then enter `FAULT`. - If the Mac/app heartbeat disappears while HP is on, begin a 2-minute safe-shutdown countdown. A valid heartbeat cancels it. At expiry, ATLAS Core performs normal OS shutdown; Sentinel does not simulate a power-button press. - USB serial through the internal hub is the authoritative Sentinel control link. Wi-Fi and Bluetooth are disabled by default. - ATLAS Core local AI runs on the HP; deterministic safety remains on Sentinel. AI can never bypass hardware limits or confirmation policy. ### 12. Required final report and acceptance gates At the end, provide one concise but complete report containing: 1. all deleted obsolete references and why; 2. all final component references, values, exact MPNs, footprints, and DNP status; 3. final GPIO-to-DevKit-header mapping; 4. timer calculation with nominal and worst-case continuous-on time; 5. HP isolation connectivity audit result; 6. ERC result and remaining warnings, if any; 7. final board dimensions, hole coordinates, layer rules, and isolation/antenna keep-outs; 8. routing completion and airwire count; 9. DRC result and remaining violations, if any; 10. populated 3D-model coverage and any missing mechanical models; 11. final PCB BOM and separate system/harness BOM; 12. exact Flux menu steps for bare-board STEP and populated-board STL/COLLADA export; 13. unresolved external mechanical inputs for the later full-computer FreeCAD assembly. Give separate `PASS` or `FAIL` for: - `SCHEMATIC_COMPLETE` - `GPIO_MAP` - `POWER_UP_FAIL_OFF` - `HARDWARE_PULSE_LIMIT` - `HP_SWITCH_ISOLATION` - `OPTICAL_STATE_ISOLATION` - `ERC` - `PCB_PLACEMENT` - `PCB_ROUTING` - `DRC` - `3D_COMPONENT_COVERAGE` - `BOARD_READY_FOR_MECHANICAL_FIT_TEST` Do not mark any item PASS without evidence from the applied project. Do not claim the full ATLAS X computer enclosure is dimensionally complete until the measured HP mechanical package is supplied. Do not generate Gerbers, pick-and-place files, or place a manufacturing order in this run. Stop after the completed routed PCB, clean DRC, validated populated-board 3D view, BOMs, mechanical handoff, and final report. Preserve the result as the project checkpoint **`AX-CTRL-REV-A-CAD-ALPHA-1`**. --- ## END MASTER PROMPT