(module VREG_TLV1117LV33DCYR (layer F.Cu) (tedit 65576914)
  (descr "")
  (attr smd)
  (fp_text reference REF** (at -0.025 -4.754 0) (layer F.SilkS))
  (fp_text value VREG_TLV1117LV33DCYR (at 9.5 4.365 0) (layer F.Fab))
  (pad 1 smd rect (at -2.9 -2.3 270.0) (size 0.95 2.15) (layers F.Cu F.Mask F.Paste) (solder_mask_margin 0.102))
  (pad 2 smd rect (at -2.9 0.0 270.0) (size 0.95 2.15) (layers F.Cu F.Mask F.Paste) (solder_mask_margin 0.102))
  (pad 3 smd rect (at -2.9 2.3 270.0) (size 0.95 2.15) (layers F.Cu F.Mask F.Paste) (solder_mask_margin 0.102))
  (pad 4 smd rect (at 2.9 0.0 270.0) (size 3.25 2.15) (layers F.Cu F.Mask F.Paste) (solder_mask_margin 0.102))
)