(module "DIP762W60P254L730H450Q6N" (layer F.Cu)
  (descr "DIP-6")
  (tags "Integrated Circuit")
  (fp_text reference IC** (at 0 0) (layer F.SilkS)
    (effects (font (size 1.27 1.27) (thickness 0.254)))
  )
  (fp_text user %R (at 0 0) (layer F.Fab)
    (effects (font (size 1.27 1.27) (thickness 0.254)))
  )
  (fp_text value "DIP762W60P254L730H450Q6N" (at 0 0) (layer F.SilkS) hide
    (effects (font (size 1.27 1.27) (thickness 0.254)))
  )
  (fp_line (start -4.81 -4.15) (end 4.81 -4.15) (layer F.CrtYd) (width 0.05))
  (fp_line (start 4.81 -4.15) (end 4.81 4.15) (layer F.CrtYd) (width 0.05))
  (fp_line (start 4.81 4.15) (end -4.81 4.15) (layer F.CrtYd) (width 0.05))
  (fp_line (start -4.81 4.15) (end -4.81 -4.15) (layer F.CrtYd) (width 0.05))
  (fp_line (start -3.5 -3.9) (end 3.5 -3.9) (layer F.Fab) (width 0.1))
  (fp_line (start 3.5 -3.9) (end 3.5 3.9) (layer F.Fab) (width 0.1))
  (fp_line (start 3.5 3.9) (end -3.5 3.9) (layer F.Fab) (width 0.1))
  (fp_line (start -3.5 3.9) (end -3.5 -3.9) (layer F.Fab) (width 0.1))
  (fp_line (start -3.5 -2.63) (end -2.23 -3.9) (layer F.Fab) (width 0.1))
  (fp_line (start -4.41 -3.9) (end 3.5 -3.9) (layer F.SilkS) (width 0.2))
  (fp_line (start -3.5 3.9) (end 3.5 3.9) (layer F.SilkS) (width 0.2))
  (pad 1 thru_hole rect (at -3.81 -2.54) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
  (pad 2 thru_hole circle (at -3.81 0) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
  (pad 3 thru_hole circle (at -3.81 2.54) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
  (pad 4 thru_hole circle (at 3.81 2.54) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
  (pad 5 thru_hole circle (at 3.81 0) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
  (pad 6 thru_hole circle (at 3.81 -2.54) (size 1.2 1.2) (drill 0.8) (layers *.Cu *.Mask))
  (model VOH1016AD.stp
    (at (xyz 0 0 0))
    (scale (xyz 1 1 1))
    (rotate (xyz 0 0 0))
  )
)