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INTERFACE CONTROL DOCUMENT -- COLD-NATIVE CARD-CAGE COMPUTE PLATFORM
ICD Rev A -- September 20, 2026
Program: Cold-Native Vertical Server Carrier (design engine project of record)
Authority: Founder-approved Architecture and Cold-Power Design Study Rev B
(Sep 20, 2026). This ICD is the standing constitution for every board designed
in this program. Every design session inherits it. Changes require explicit
Founder approval and a revision letter.
NOTE: This document is written vendor-neutral and platform-neutral by intent.
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1. PROGRAM CHARTER (summary)
1.1 The platform is a sealed, dry-nitrogen, sub-zero, conduction-cooled
    vertical card-cage compute system. Boards are clamped between liquid
    cold plates (sandwich architecture). There is no air cooling anywhere.
1.2 Program board set, in build order: (1) power spine / bus interface,
    (2) card-cage backplane, (3) supervisory governance controller
    [first fabricated prototype], (4) Slot Class A compute carrier,
    (5) supporting citizens as defined.
1.3 Performance doctrine: maximum sustained compute throughput and minimum
    host-to-accelerator latency. The supervisory controller may limit
    performance for safety; the carrier power tree shall not be the normal
    performance limiter.
1.4 Design-for-validation doctrine: simulation retires design risk;
    hardware retires qualification risk. No performance or reliability
    claim is made beyond the validation rung actually completed.

2. ENVIRONMENT
2.1 Operating ambient (enclosure): -20 C. Study excursion: -40 C
    (qualification mode only until every part and process is qualified).
2.2 Atmosphere: sealed dry nitrogen. Condensation control (dew point,
    purge, door-open recovery, moisture sensing) is a chassis requirement.
2.3 Cooling: conductive only. Cold plates contact module heat spreaders,
    die pedestals, and converter thermal lands. The PCB is never the
    primary heat spreader.
2.4 Orientation: vertical, blind-mate insertion into card cage.

3. BUS AND POWER DEFINITION (RATIFIED)
3.1 Cage bus: 48 V DC nominal, OCP/ORv3-style blind-mate busbar interface.
3.2 Module compatibility window: 44-59.5 V (OAM r2.0 high-power input);
    plant nominal and transients coordinated below the 59.5/60 V ceiling
    and hot-swap/TVS limits.
3.3 Slot Class A (frozen): 1.5 kW nominal, 1.8 kW peak. Card interface
    sized for at least 45 A continuous at 44 V low-line (raw 1.8 kW
    low-line current 40.9 A) before connector derating.
3.4 Slot Class B (backplane placeholder only): ~3 kW future slot. Reserve
    connector-family path to approximately 70 A via additional power
    blades or double-width slot. No Class B card hardware is designed,
    installed, or sized on Class A cards.
3.5 Connector doctrine: separate positive/return power blades; protective
    chassis contact mates FIRST / breaks LAST; presence/power-kill contact
    mates LAST / breaks FIRST; independent management contacts.
3.6 Protection stack per card: slot/source fuse coordination, hot-swap
    controller (80 V class, external FETs, PMBus telemetry), UV/OV,
    inrush limiting, reverse-energy blocking as required, hardware kill
    independent of host firmware.
3.7 Conversion doctrine: 48 V delivered DIRECT to the accelerator module.
    Regulated 12 V generated locally only for the CPU module (fixed 12 V
    input standard) and auxiliaries, via paralleled conduction-cooled
    converter modules. Accelerator power is never converted to 12 V.
3.8 Always-on domain: isolated housekeeping rails (12 V AON, 5 V, 3.3 V)
    powering the supervisory controller independent of payload state.

4. COMPUTE MODULE BASELINES (RATIFIED)
4.1 CPU: COM-HPC Server Type Size D/E module, extended-temperature SKU
    explicitly ordered with -40 C minimum Tcase rating (industrial
    Xeon D class per Rev B citation). Commercial 0 C-minimum modules are
    a later variant behind qualification. 358 W module input ceiling.
4.2 Accelerator: OAM r2.0, vendor-agnostic. Carry AMD Instinct-class
    (750 W, 54 V) and Intel Gaudi-class (up to 900 W) envelopes until
    module selection. NVIDIA is out of carrier scope except as a
    purchased vendor baseboard, which enters the cage as its own citizen.
4.3 Vendor power stages remain on their modules. The carrier never
    recreates module-internal voltage regulation.

5. WARM ADMISSION AND THERMAL GOVERNANCE (RATIFIED)
5.1 Admission floor: all boot-critical sensors at or above +5 C.
    Release threshold +7 C with 2 C hysteresis.
5.2 Sequence: always-on domain only at insertion; enclosure validation
    (dry-gas indication, no leak/condensation alarm, coolant flow,
    plausible sensors, plates present); warm-soak to threshold; enable
    protected 48 V payload; enable conversion and standby rails; release
    CPU reset; verify telemetry; enumerate accelerator; then authorized
    staged cooldown to -20 C in bounded steps under rate-of-change,
    minimum-temperature, rail-margin, and link-error-counter supervision.
5.3 Any sensor below validated floor, telemetry loss, flow loss, leak
    indication, or rail excursion: throttle, controlled shutdown, payload
    isolation. Hardware kill path functions without host firmware.
5.4 Warm-up energy (heaters or warm coolant) is a chassis function; the
    card commands and verifies, never supplies.
5.5 The supervisory controller must start reliably at -40 C even though
    compute admission waits for +5 C.

6. HIGH-SPEED AND STACKUP STANDARD (RATIFIED, PRE-LAYOUT)
6.1 Laminate: Megtron-6-class ultra-low-loss family with HVLP copper
    (preferred R-5775(N)/R-5670(N); halogen-free R-5375(N) alternate if
    fabricator-qualified). Low-temperature coupons mandatory.
6.2 Stackup family: 14-18 copper layers; at least four solid ground
    references; dedicated 48 V and 12 V distribution layers; paired
    stripline for Gen5 escape. Final count follows module pin maps and
    fabricator field solve.
6.3 Channel doctrine: PCIe Gen5 x16 host link, 85 ohm differential
    stripline, no plane splits, back-drilled vias, matched via structures.
6.4 Retimer-elimination geometry: CPU-module PCIe edge placed directly
    opposite the accelerator host-link connector, lane fields facing
    inward; one direct segment, no riser, no cable, no intermediate
    connector. Provisional routed-length goal 100 mm or less, hard design
    review at 125 mm, subject to mechanical feasibility; validated by
    correlated channel simulation with 10-20 percent loss margin before
    the topology is frozen.
6.5 Passenger doctrine: single boot NVMe only; no general storage
    expansion; no legacy I/O; no peripheral controllers that backplane
    management can serve.

7. TELEMETRY MAP (MINIMUM SENSOR SET)
    Each converter bank; each module power-entry region; CPU pedestal
    edge; accelerator pedestal edge; coolant inlet; coolant outlet; both
    plate edge regions; card leading edge; backplane connector region;
    one board-center reference. Distributed digital sensors plus module
    telemetry plus redundant analog trips. Sensor accuracy below 0 C is
    a budgeted item (IC accuracy, gradients, attachment, calibration).

8. COLD-RATED BOM LAW
8.1 No liquid aluminum electrolytic capacitors anywhere. Conductive
    polymer, polymer tantalum, film, and MLCC arrays; every MPN verified
    to category minimum of -40 C or below.
8.2 MLCC: X7R/X8R or C0G/NP0; capacitance verified across DC bias and
    -40 C; minimum 2x nominal design allowance.
8.3 Timing: TCXO or qualified XO rated -40 C or below; no bare crystals.
8.4 RTC: backplane-powered always-on preferred; else -40 C supercapacitor
    or relocated energy source. No coin cells in the sealed enclosure.
8.5 Connectors: every mated stack verified by written -40 C rating
    (plastics, plating, contact force, cycle life).
8.6 Conformal coat: low-modulus silicone class with verified thermal
    shock; connectors and thermal interfaces masked.
8.7 Inductors, shunts, precision networks: cold behavior verified per
    part (permeability, TCR drift at thresholds, mechanical bonding).
8.8 Assembly: lead-free alloy and land patterns validated by
    thermal-cycle coupons; the dominant reliability risk is repeated CTE
    strain, not steady cold.

9. MECHANICAL DOCTRINE
9.1 Clamp force closes through metal spacers/standoffs and perimeter
    through-bolts, never through unsupported PCB.
9.2 Perimeter stiffener frame plus local load-spreader frames at module
    connectors; no pedestal load through mezzanine connectors.
9.3 Study boss pattern: perimeter 40-60 mm spacing, reinforced at module
    long edges and symmetric about each die pedestal; final pattern by
    module drawings and plate FEA.
9.4 Die pedestals carry compliant replaceable thermal interface with hard
    compression stop; parallelism, flatness, and connector stack analyzed
    together.
9.5 Vertical extraction loads (guides, handles, blind-mate forces,
    cold-line couplings, plate mass) are chassis design inputs.

10. GOVERNANCE AND GATES
10.1 Layout gate: no component placement or routing until the schematic
     architecture is approved against this ICD.
10.2 Sourcing rule: temperature ratings and standards claims carry part
     numbers or citations; anything unverified is logged as an open
     assumption, never asserted.
10.3 The Rev B assumptions register (45 items) is the standing validation
     job-jar; retiring items follows the validation ladder (simulation,
     component cold-soak, eval boards, stackup coupons, governance
     controller prototype, carrier).
10.4 Air-cooling conventions are deleted design rules. Any reappearance
     is a defect.
10.5 This ICD is amended only by Founder-approved revision. Sessions cite
     the ICD revision they were built against.

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ICD Rev A end. Program constitution effective September 20, 2026.
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